Initial Subzero WASM prototype.

src/IceCfgNode.cpp

 //===- subzero/src/IceCfgNode.cpp - Basic block (node) implementation -----===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 19 matching lines @@
   if (BuildDefs::dump()) {
     Name =
         NodeString::createWithString(Func, "__" + std::to_string(getIndex()));
   } else {
     Name = NodeString::createWithoutString(Func);
   }
 }
 
 // Adds an instruction to either the Phi list or the regular instruction list.
 // Validates that all Phis are added before all regular instructions.
-void CfgNode::appendInst(Inst *Instr) {
+void CfgNode::appendInst(Inst *Instr, bool AllowPhisAnywhere) {
   ++InstCountEstimate;
+
+  if (auto *Br = llvm::dyn_cast<InstBr>(Instr)) {

[Jim Stichnoth, 2016/04/04 21:26:51]

You may also want to do the same for switch instructions.

If it's a branch or switch (or any other terminator instruction), you could
iterate over Instr->getTerminatorEdges() and add the out-edges.

Also, I think it would be better if this block were guarded on wasm, e.g.
BuildDefs::wasm(), or getFlags().wasm() or whatever it's called.

[Eric Holk, 2016/04/04 22:23:22]

Done.

+    if (auto *N = Br->getTargetTrue()) {
+      N->addInEdge(this);
+      addOutEdge(N);
+    }
+    if (auto *N = Br->getTargetFalse()) {
+      N->addInEdge(this);
+      addOutEdge(N);
+    }
+  }
+
   if (auto *Phi = llvm::dyn_cast<InstPhi>(Instr)) {
-    if (!Insts.empty()) {
+    if (!AllowPhisAnywhere && !Insts.empty()) {
       Func->setError("Phi instruction added to the middle of a block");
       return;
     }
     Phis.push_back(Phi);
   } else {
     Insts.push_back(Instr);
   }
 }
 
 namespace {
@@ skipping 20 matching lines @@
 
 // When a node is created, the OutEdges are immediately known, but the InEdges
 // have to be built up incrementally. After the CFG has been constructed, the
 // computePredecessors() pass finalizes it by creating the InEdges list.
 void CfgNode::computePredecessors() {
   for (CfgNode *Succ : OutEdges)
     Succ->InEdges.push_back(this);
 }
 
 void CfgNode::computeSuccessors() {
+  OutEdges.clear();
+  InEdges.clear();
   OutEdges = Insts.rbegin()->getTerminatorEdges();
 }
 
 // Validate each Phi instruction in the node with respect to control flow. For
 // every phi argument, its label must appear in the predecessor list. For each
 // predecessor, there must be a phi argument with that label. We don't check
 // that phi arguments with the same label have the same value.
 void CfgNode::validatePhis() {
   for (Inst &Instr : Phis) {
     auto *Phi = llvm::cast<InstPhi>(&Instr);
@@ skipping 781 matching lines @@
     if (I.isDeleted())
       continue;
     if (I.isUnconditionalBranch())
       Branch = &I;
     else if (!I.isRedundantAssign())
       return;
   }
   // Make sure there is actually a successor to repoint in-edges to.
   if (OutEdges.empty())
     return;
-  assert(OutEdges.size() == 1);
+  assert(hasSingleOutEdge());
   // Don't try to delete a self-loop.
   if (OutEdges[0] == this)
     return;
   // Make sure the node actually contains (ends with) an unconditional branch.
   if (Branch == nullptr)
     return;
 
   Branch->setDeleted();
   CfgNode *Successor = OutEdges.front();
   // Repoint all this node's in-edges to this node's successor, unless this
@@ skipping 560 matching lines @@
   auto *Instr = InstIntrinsicCall::create(
       Func, 5, Func->makeVariable(IceType_i64), RMWI64Name, Info->Info);
   Instr->addArg(AtomicRMWOp);
   Instr->addArg(Counter);
   Instr->addArg(One);
   Instr->addArg(OrderAcquireRelease);
   Insts.push_front(Instr);
 }
 
 } // end of namespace Ice