S390: Impl Left/Right Logical/Arith Shift Pair

src/s390/assembler-s390.cc

Index: src/s390/assembler-s390.cc
diff --git a/src/s390/assembler-s390.cc b/src/s390/assembler-s390.cc
index 0c5f79cbf393d0122dfa4ab2e498aa8e73f78883..e4d63a855d64852f10160a67d2b9f99ef6daeace 100644
--- a/src/s390/assembler-s390.cc
+++ b/src/s390/assembler-s390.cc
@@ -2336,12 +2336,30 @@ void Assembler::sllg(Register r1, Register r3, const Operand& opnd) {
   rsy_form(SLLG, r1, r3, r0, opnd.immediate());
 }
 
+// Shift Left Double Logical (64)
+void Assembler::sldl(Register r1, Register b2, const Operand& opnd) {
+  DCHECK(r1.code() % 2 == 0);
+  rs_form(SLDL, r1, r0, b2, opnd.immediate());
+}
+
 // Shift Right Single Logical (32)
 void Assembler::srl(Register r1, Register opnd) {
   DCHECK(!opnd.is(r0));
   rs_form(SRL, r1, r0, opnd, 0);
 }
 
+// Shift Right Double Arith (64)
+void Assembler::srda(Register r1, Register b2, const Operand& opnd) {
+  DCHECK(r1.code() % 2 == 0);
+  rs_form(SRDA, r1, r0, b2, opnd.immediate());
+}
+
+// Shift Right Double Logical (64)
+void Assembler::srdl(Register r1, Register b2, const Operand& opnd) {
+  DCHECK(r1.code() % 2 == 0);
+  rs_form(SRDL, r1, r0, b2, opnd.immediate());
+}
+
 // Shift Right Single Logical (32)
 void Assembler::srl(Register r1, const Operand& opnd) {
   rs_form(SRL, r1, r0, r0, opnd.immediate());