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1 // Copyright 2014 the V8 project authors. All rights reserved. | 1 // Copyright 2014 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 // A Disassembler object is used to disassemble a block of code instruction by | 5 // A Disassembler object is used to disassemble a block of code instruction by |
6 // instruction. The default implementation of the NameConverter object can be | 6 // instruction. The default implementation of the NameConverter object can be |
7 // overriden to modify register names or to do symbol lookup on addresses. | 7 // overriden to modify register names or to do symbol lookup on addresses. |
8 // | 8 // |
9 // The example below will disassemble a block of code and print it to stdout. | 9 // The example below will disassemble a block of code and print it to stdout. |
10 // | 10 // |
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636 break; | 636 break; |
637 case SRL: | 637 case SRL: |
638 Format(instr, "srl\t'r1,'d1('r3)"); | 638 Format(instr, "srl\t'r1,'d1('r3)"); |
639 break; | 639 break; |
640 case SLA: | 640 case SLA: |
641 Format(instr, "sla\t'r1,'d1('r3)"); | 641 Format(instr, "sla\t'r1,'d1('r3)"); |
642 break; | 642 break; |
643 case SRA: | 643 case SRA: |
644 Format(instr, "sra\t'r1,'d1('r3)"); | 644 Format(instr, "sra\t'r1,'d1('r3)"); |
645 break; | 645 break; |
| 646 case SLDL: |
| 647 Format(instr, "sldl\t'r1,'d1('r3)"); |
| 648 break; |
646 case AGR: | 649 case AGR: |
647 Format(instr, "agr\t'r5,'r6"); | 650 Format(instr, "agr\t'r5,'r6"); |
648 break; | 651 break; |
649 case AGFR: | 652 case AGFR: |
650 Format(instr, "agfr\t'r5,'r6"); | 653 Format(instr, "agfr\t'r5,'r6"); |
651 break; | 654 break; |
652 case ARK: | 655 case ARK: |
653 Format(instr, "ark\t'r5,'r6,'r3"); | 656 Format(instr, "ark\t'r5,'r6,'r3"); |
654 break; | 657 break; |
655 case AGRK: | 658 case AGRK: |
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961 case SQDBR: | 964 case SQDBR: |
962 Format(instr, "sqdbr\t'f5,'f6"); | 965 Format(instr, "sqdbr\t'f5,'f6"); |
963 break; | 966 break; |
964 case LCDBR: | 967 case LCDBR: |
965 Format(instr, "lcdbr\t'f5,'f6"); | 968 Format(instr, "lcdbr\t'f5,'f6"); |
966 break; | 969 break; |
967 case STH: | 970 case STH: |
968 Format(instr, "sth\t'r1,'d1('r2d,'r3)"); | 971 Format(instr, "sth\t'r1,'d1('r2d,'r3)"); |
969 break; | 972 break; |
970 case SRDA: | 973 case SRDA: |
971 Format(instr, "srda\t'r1,'d1"); | 974 Format(instr, "srda\t'r1,'d1('r3)"); |
972 break; | 975 break; |
973 case SRDL: | 976 case SRDL: |
974 Format(instr, "srdl\t'r1,'d1"); | 977 Format(instr, "srdl\t'r1,'d1('r3)"); |
975 break; | 978 break; |
976 case MADBR: | 979 case MADBR: |
977 Format(instr, "madbr\t'f3,'f5,'f6"); | 980 Format(instr, "madbr\t'f3,'f5,'f6"); |
978 break; | 981 break; |
979 case MSDBR: | 982 case MSDBR: |
980 Format(instr, "msdbr\t'f3,'f5,'f6"); | 983 Format(instr, "msdbr\t'f3,'f5,'f6"); |
981 break; | 984 break; |
982 case FLOGR: | 985 case FLOGR: |
983 Format(instr, "flogr\t'r5,'r6"); | 986 Format(instr, "flogr\t'r5,'r6"); |
984 break; | 987 break; |
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1393 byte* prev_pc = pc; | 1396 byte* prev_pc = pc; |
1394 pc += d.InstructionDecode(buffer, pc); | 1397 pc += d.InstructionDecode(buffer, pc); |
1395 v8::internal::PrintF(f, "%p %08x %s\n", prev_pc, | 1398 v8::internal::PrintF(f, "%p %08x %s\n", prev_pc, |
1396 *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); | 1399 *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); |
1397 } | 1400 } |
1398 } | 1401 } |
1399 | 1402 |
1400 } // namespace disasm | 1403 } // namespace disasm |
1401 | 1404 |
1402 #endif // V8_TARGET_ARCH_S390 | 1405 #endif // V8_TARGET_ARCH_S390 |
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