S390: Impl Left/Right Logical/Arith Shift Pair

src/s390/assembler-s390.cc

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions
 // are met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 2318 matching lines @@
 void Assembler::sllg(Register r1, Register r3, Register opnd) {
   DCHECK(!opnd.is(r0));
   rsy_form(SLLG, r1, r3, opnd, 0);
 }
 
 // Shift Left Single Logical (64)
 void Assembler::sllg(Register r1, Register r3, const Operand& opnd) {
   rsy_form(SLLG, r1, r3, r0, opnd.immediate());
 }
 
+// Shift Left Double Logical (64)
+void Assembler::sldl(Register r1, Register b2, const Operand& opnd) {
+  DCHECK(r1.code() % 2 == 0);
+  rs_form(SLDL, r1, r0, b2, opnd.immediate());
+}
+
 // Shift Right Single Logical (32)
 void Assembler::srl(Register r1, Register opnd) {
   DCHECK(!opnd.is(r0));
   rs_form(SRL, r1, r0, opnd, 0);
 }
 
+// Shift Right Double Arith (64)
+void Assembler::srda(Register r1, Register b2, const Operand& opnd) {
+  DCHECK(r1.code() % 2 == 0);
+  rs_form(SRDA, r1, r0, b2, opnd.immediate());
+}
+
+// Shift Right Double Logical (64)
+void Assembler::srdl(Register r1, Register b2, const Operand& opnd) {
+  DCHECK(r1.code() % 2 == 0);
+  rs_form(SRDL, r1, r0, b2, opnd.immediate());
+}
+
 // Shift Right Single Logical (32)
 void Assembler::srl(Register r1, const Operand& opnd) {
   rs_form(SRL, r1, r0, r0, opnd.immediate());
 }
 
 // Shift Right Single Logical (32)
 void Assembler::srlk(Register r1, Register r3, Register opnd) {
   DCHECK(!opnd.is(r0));
   rsy_form(SRLK, r1, r3, opnd, 0);
 }
@@ skipping 676 matching lines @@
 
     reloc_info_writer.Write(&rinfo);
   }
 
   reloc_info_writer.Finish();
 }
 
 }  // namespace internal
 }  // namespace v8
 #endif  // V8_TARGET_ARCH_S390