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| 1 // Copyright 2012 the V8 project authors. All rights reserved. | 1 // Copyright 2012 the V8 project authors. All rights reserved. |
| 2 // Redistribution and use in source and binary forms, with or without | 2 // Redistribution and use in source and binary forms, with or without |
| 3 // modification, are permitted provided that the following conditions are | 3 // modification, are permitted provided that the following conditions are |
| 4 // met: | 4 // met: |
| 5 // | 5 // |
| 6 // * Redistributions of source code must retain the above copyright | 6 // * Redistributions of source code must retain the above copyright |
| 7 // notice, this list of conditions and the following disclaimer. | 7 // notice, this list of conditions and the following disclaimer. |
| 8 // * Redistributions in binary form must reproduce the above | 8 // * Redistributions in binary form must reproduce the above |
| 9 // copyright notice, this list of conditions and the following | 9 // copyright notice, this list of conditions and the following |
| 10 // disclaimer in the documentation and/or other materials provided | 10 // disclaimer in the documentation and/or other materials provided |
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| 212 // combinations are possible. | 212 // combinations are possible. |
| 213 | 213 |
| 214 if (source->IsRegister()) { | 214 if (source->IsRegister()) { |
| 215 Register source_register = cgen_->ToRegister(source); | 215 Register source_register = cgen_->ToRegister(source); |
| 216 if (destination->IsRegister()) { | 216 if (destination->IsRegister()) { |
| 217 __ mov(cgen_->ToRegister(destination), source_register); | 217 __ mov(cgen_->ToRegister(destination), source_register); |
| 218 } else { | 218 } else { |
| 219 ASSERT(destination->IsStackSlot()); | 219 ASSERT(destination->IsStackSlot()); |
| 220 __ str(source_register, cgen_->ToMemOperand(destination)); | 220 __ str(source_register, cgen_->ToMemOperand(destination)); |
| 221 } | 221 } |
| 222 |
| 222 } else if (source->IsStackSlot()) { | 223 } else if (source->IsStackSlot()) { |
| 223 MemOperand source_operand = cgen_->ToMemOperand(source); | 224 MemOperand source_operand = cgen_->ToMemOperand(source); |
| 224 if (destination->IsRegister()) { | 225 if (destination->IsRegister()) { |
| 225 __ ldr(cgen_->ToRegister(destination), source_operand); | 226 __ ldr(cgen_->ToRegister(destination), source_operand); |
| 226 } else { | 227 } else { |
| 227 ASSERT(destination->IsStackSlot()); | 228 ASSERT(destination->IsStackSlot()); |
| 228 MemOperand destination_operand = cgen_->ToMemOperand(destination); | 229 MemOperand destination_operand = cgen_->ToMemOperand(destination); |
| 229 if (in_cycle_) { | 230 if (in_cycle_) { |
| 230 if (!destination_operand.OffsetIsUint12Encodable()) { | 231 if (!destination_operand.OffsetIsUint12Encodable()) { |
| 231 // ip is overwritten while saving the value to the destination. | 232 // ip is overwritten while saving the value to the destination. |
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| 247 LConstantOperand* constant_source = LConstantOperand::cast(source); | 248 LConstantOperand* constant_source = LConstantOperand::cast(source); |
| 248 if (destination->IsRegister()) { | 249 if (destination->IsRegister()) { |
| 249 Register dst = cgen_->ToRegister(destination); | 250 Register dst = cgen_->ToRegister(destination); |
| 250 if (cgen_->IsSmi(constant_source)) { | 251 if (cgen_->IsSmi(constant_source)) { |
| 251 __ mov(dst, Operand(cgen_->ToSmi(constant_source))); | 252 __ mov(dst, Operand(cgen_->ToSmi(constant_source))); |
| 252 } else if (cgen_->IsInteger32(constant_source)) { | 253 } else if (cgen_->IsInteger32(constant_source)) { |
| 253 __ mov(dst, Operand(cgen_->ToInteger32(constant_source))); | 254 __ mov(dst, Operand(cgen_->ToInteger32(constant_source))); |
| 254 } else { | 255 } else { |
| 255 __ LoadObject(dst, cgen_->ToHandle(constant_source)); | 256 __ LoadObject(dst, cgen_->ToHandle(constant_source)); |
| 256 } | 257 } |
| 257 } else if (source->IsDoubleRegister()) { | |
| 258 DwVfpRegister result = cgen_->ToDoubleRegister(destination); | |
| 259 double v = cgen_->ToDouble(constant_source); | |
| 260 __ Vmov(result, v, ip); | |
| 261 } else { | 258 } else { |
| 262 ASSERT(destination->IsStackSlot()); | 259 ASSERT(destination->IsStackSlot()); |
| 263 ASSERT(!in_cycle_); // Constant moves happen after all cycles are gone. | 260 ASSERT(!in_cycle_); // Constant moves happen after all cycles are gone. |
| 264 if (cgen_->IsSmi(constant_source)) { | 261 if (cgen_->IsSmi(constant_source)) { |
| 265 __ mov(kSavedValueRegister, Operand(cgen_->ToSmi(constant_source))); | 262 __ mov(kSavedValueRegister, Operand(cgen_->ToSmi(constant_source))); |
| 266 } else if (cgen_->IsInteger32(constant_source)) { | 263 } else if (cgen_->IsInteger32(constant_source)) { |
| 267 __ mov(kSavedValueRegister, | 264 __ mov(kSavedValueRegister, |
| 268 Operand(cgen_->ToInteger32(constant_source))); | 265 Operand(cgen_->ToInteger32(constant_source))); |
| 269 } else { | 266 } else { |
| 270 __ LoadObject(kSavedValueRegister, | 267 __ LoadObject(kSavedValueRegister, |
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| 309 UNREACHABLE(); | 306 UNREACHABLE(); |
| 310 } | 307 } |
| 311 | 308 |
| 312 moves_[index].Eliminate(); | 309 moves_[index].Eliminate(); |
| 313 } | 310 } |
| 314 | 311 |
| 315 | 312 |
| 316 #undef __ | 313 #undef __ |
| 317 | 314 |
| 318 } } // namespace v8::internal | 315 } } // namespace v8::internal |
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