Adds support for integer division for ARM chips without the sdiv instruction.

runtime/vm/assembler_arm.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"
 #if defined(TARGET_ARCH_ARM)
 
 #include "vm/assembler.h"
 #include "vm/simulator.h"
 #include "vm/runtime_entry.h"
@@ skipping 1925 matching lines @@
   if (ShifterOperand::CanHold(value, &shifter_op)) {
     cmp(rn, shifter_op, cond);
   } else {
     ASSERT(rn != IP);
     LoadImmediate(IP, value, cond);
     cmp(rn, ShifterOperand(IP), cond);
   }
 }
 
 
+void Assembler::IntegerDivide(Register result, Register left, Register right,
+                              DRegister tmpl, DRegister tmpr) {
+  // tmpl can't be DTMP because we subsequently use STMP, but tmpr can be
+  // DTMP because we do the divide immediately after writing it.
+  ASSERT(tmpl != DTMP);
+  if (CPUFeatures::integer_division_supported()) {
+    sdiv(result, left, right);
+  } else {
+    vmovsr(STMP, left);

[regis, 2013/07/01 16:54:09]

STMP -> static_cast<SRegister>(2 * tmpl)
ditto for the right operand.

[zra, 2013/07/01 17:43:46]

Done.

+    vcvtdi(tmpl, STMP);  // left is in tmpl.
+    vmovsr(STMP, right);
+    vcvtdi(tmpr, STMP);  // right is in tmpr.
+    vdivd(tmpr, tmpl, tmpr);
+    vcvtid(STMP, tmpr);
+    vmovrs(result, STMP);
+  }
+}
+
+
 static int NumRegsBelowFP(RegList regs) {
   int count = 0;
   for (int i = 0; i < FP; i++) {
     if ((regs & (1 << i)) != 0) {
       count++;
     }
   }
   return count;
 }
 
@@ skipping 260 matching lines @@
 
 const char* Assembler::FpuRegisterName(FpuRegister reg) {
   ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters));
   return fpu_reg_names[reg];
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM