test/CodeGen/PowerPC/crsave.ll - Issue 183273009: Prep for merging 3.4: Undo changes from 3.3 branch

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Issue 183273009: Prep for merging 3.4: Undo changes from 3.3 branch (Closed) Base URL: http://git.chromium.org/native_client/pnacl-llvm.git@master

Patch Set: Retry Created 6 years, 9 months ago

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1 ; RUN: llc -O0 -disable-fp-elim -mtriple=powerpc-unknown-linux-gnu < %s \| FileCh eck %s -check-prefix=PPC32	1 ; RUN: llc -O0 -disable-fp-elim -mtriple=powerpc-unknown-linux-gnu < %s \| FileCh eck %s -check-prefix=PPC32

2 ; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu < %s \| FileCheck %s -check-p refix=PPC64	2 ; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu < %s \| FileCheck %s -check-p refix=PPC64

3	3

4 declare void @foo()	4 declare void @foo()

5	5

6 define i32 @test_cr2() nounwind {	6 define i32 @test_cr2() nounwind {

7 entry:	7 entry:

8 %ret = alloca i32, align 4	8 %ret = alloca i32, align 4

9 %0 = call i32 asm sideeffect "\0A\09mtcr $4\0A\09cmp 2,$2,$1\0A\09mfcr $0", "= r,r,r,r,r,~{cr2}"(i32 1, i32 2, i32 3, i32 0) nounwind	9 %0 = call i32 asm sideeffect "\0A\09mtcr $4\0A\09cmp 2,$2,$1\0A\09mfcr $0", "= r,r,r,r,r,~{cr2}"(i32 1, i32 2, i32 3, i32 0) nounwind

10 store i32 %0, i32* %ret, align 4	10 store i32 %0, i32* %ret, align 4

11 call void @foo()	11 call void @foo()

12 %1 = load i32* %ret, align 4	12 %1 = load i32* %ret, align 4

13 ret i32 %1	13 ret i32 %1

14 }	14 }

15	15

16 ; PPC32: stw 31, -4(1)

17 ; PPC32: stwu 1, -32(1)

18 ; PPC32: mfcr 12	16 ; PPC32: mfcr 12

19 ; PPC32-NEXT: stw 12, 24(31)	17 ; PPC32-NEXT: stw 12, {{[0-9]+}}(31)

20 ; PPC32: lwz 12, 24(31)	18 ; PPC32: lwz 12, {{[0-9]+}}(31)

21 ; PPC32-NEXT: mtcrf 32, 12	19 ; PPC32-NEXT: mtcrf 32, 12

22	20

23 ; PPC64: mfcr 12	21 ; PPC64: mfcr 12

24 ; PPC64: stw 12, 8(1)	22 ; PPC64: stw 12, 8(1)

25 ; PPC64: stdu 1, -[[AMT:[0-9]+]](1)	23 ; PPC64: stdu 1, -[[AMT:[0-9]+]](1)

26 ; PPC64: addi 1, 1, [[AMT]]	24 ; PPC64: addi 1, 1, [[AMT]]

27 ; PPC64: lwz 12, 8(1)	25 ; PPC64: lwz 12, 8(1)

28 ; PPC64: mtcrf 32, 12	26 ; PPC64: mtcrf 32, 12

29	27

30 define i32 @test_cr234() nounwind {	28 define i32 @test_cr234() nounwind {

31 entry:	29 entry:

32 %ret = alloca i32, align 4	30 %ret = alloca i32, align 4

33 %0 = call i32 asm sideeffect "\0A\09mtcr $4\0A\09cmp 2,$2,$1\0A\09cmp 3,$2,$2\ 0A\09cmp 4,$2,$3\0A\09mfcr $0", "=r,r,r,r,r,~{cr2},~{cr3},~{cr4}"(i32 1, i32 2, i32 3, i32 0) nounwind	31 %0 = call i32 asm sideeffect "\0A\09mtcr $4\0A\09cmp 2,$2,$1\0A\09cmp 3,$2,$2\ 0A\09cmp 4,$2,$3\0A\09mfcr $0", "=r,r,r,r,r,~{cr2},~{cr3},~{cr4}"(i32 1, i32 2, i32 3, i32 0) nounwind

34 store i32 %0, i32* %ret, align 4	32 store i32 %0, i32* %ret, align 4

35 call void @foo()	33 call void @foo()

36 %1 = load i32* %ret, align 4	34 %1 = load i32* %ret, align 4

37 ret i32 %1	35 ret i32 %1

38 }	36 }

39	37

40 ; PPC32: stw 31, -4(1)

41 ; PPC32: stwu 1, -32(1)

42 ; PPC32: mfcr 12	38 ; PPC32: mfcr 12

43 ; PPC32-NEXT: stw 12, 24(31)	39 ; PPC32-NEXT: stw 12, {{[0-9]+}}(31)

44 ; PPC32: lwz 12, 24(31)	40 ; PPC32: lwz 12, {{[0-9]+}}(31)

45 ; PPC32-NEXT: mtcrf 32, 12	41 ; PPC32-NEXT: mtcrf 32, 12

46 ; PPC32-NEXT: mtcrf 16, 12	42 ; PPC32-NEXT: mtcrf 16, 12

47 ; PPC32-NEXT: mtcrf 8, 12	43 ; PPC32-NEXT: mtcrf 8, 12

48	44

49 ; PPC64: mfcr 12	45 ; PPC64: mfcr 12

50 ; PPC64: stw 12, 8(1)	46 ; PPC64: stw 12, 8(1)

51 ; PPC64: stdu 1, -[[AMT:[0-9]+]](1)	47 ; PPC64: stdu 1, -[[AMT:[0-9]+]](1)

52 ; PPC64: addi 1, 1, [[AMT]]	48 ; PPC64: addi 1, 1, [[AMT]]

53 ; PPC64: lwz 12, 8(1)	49 ; PPC64: lwz 12, 8(1)

54 ; PPC64: mtcrf 32, 12	50 ; PPC64: mtcrf 32, 12

55 ; PPC64: mtcrf 16, 12	51 ; PPC64: mtcrf 16, 12

56 ; PPC64: mtcrf 8, 12	52 ; PPC64: mtcrf 8, 12

57	53

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