Prep for merging 3.4: Undo changes from 3.3 branch

lib/Target/R600/R600Instructions.td

 //===-- R600Instructions.td - R600 Instruction defs  -------*- tablegen -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // R600 Tablegen instruction definitions
@@ skipping 1597 matching lines @@
   //
   // (0, 8)           = (Input << 24) >> 24  = (Input &  0xff)       >> 0
   // (8, 8)           = (Input << 16) >> 24  = (Input &  0xffff)     >> 8
   // (16,8)           = (Input <<  8) >> 24  = (Input &  0xffffff)   >> 16
   // (24,8)           = (Input <<  0) >> 24  = (Input &  0xffffffff) >> 24
   def BFE_UINT_eg : R600_3OP <0x4, "BFE_UINT",
     [(set i32:$dst, (int_AMDIL_bit_extract_u32 i32:$src0, i32:$src1,
                                                i32:$src2))],
     VecALU
   >;
-  def : BFEPattern <BFE_UINT_eg>;
 
   def BFI_INT_eg : R600_3OP <0x06, "BFI_INT", [], VecALU>;
   defm : BFIPatterns <BFI_INT_eg>;
 
   def BIT_ALIGN_INT_eg : R600_3OP <0xC, "BIT_ALIGN_INT",
     [(set i32:$dst, (AMDGPUbitalign i32:$src0, i32:$src1, i32:$src2))],
     VecALU
   >;
 
   def MULADD_eg : MULADD_Common<0x14>;
@@ skipping 799 matching lines @@
 
 def : BitConvert <i32, f32, R600_Reg32>;
 def : BitConvert <f32, i32, R600_Reg32>;
 def : BitConvert <v4f32, v4i32, R600_Reg128>;
 def : BitConvert <v4i32, v4f32, R600_Reg128>;
 
 // DWORDADDR pattern
 def : DwordAddrPat  <i32, R600_Reg32>;
 
 } // End isR600toCayman Predicate