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| 1 //===-- R600ISelLowering.cpp - R600 DAG Lowering Implementation -----------===// | 1 //===-- R600ISelLowering.cpp - R600 DAG Lowering Implementation -----------===// |
| 2 // | 2 // |
| 3 // The LLVM Compiler Infrastructure | 3 // The LLVM Compiler Infrastructure |
| 4 // | 4 // |
| 5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
| 6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
| 7 // | 7 // |
| 8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
| 9 // | 9 // |
| 10 /// \file | 10 /// \file |
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| 36 | 36 |
| 37 setOperationAction(ISD::FADD, MVT::v4f32, Expand); | 37 setOperationAction(ISD::FADD, MVT::v4f32, Expand); |
| 38 setOperationAction(ISD::FMUL, MVT::v4f32, Expand); | 38 setOperationAction(ISD::FMUL, MVT::v4f32, Expand); |
| 39 setOperationAction(ISD::FDIV, MVT::v4f32, Expand); | 39 setOperationAction(ISD::FDIV, MVT::v4f32, Expand); |
| 40 setOperationAction(ISD::FSUB, MVT::v4f32, Expand); | 40 setOperationAction(ISD::FSUB, MVT::v4f32, Expand); |
| 41 | 41 |
| 42 setOperationAction(ISD::ADD, MVT::v4i32, Expand); | 42 setOperationAction(ISD::ADD, MVT::v4i32, Expand); |
| 43 setOperationAction(ISD::AND, MVT::v4i32, Expand); | 43 setOperationAction(ISD::AND, MVT::v4i32, Expand); |
| 44 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Expand); | 44 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Expand); |
| 45 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Expand); | 45 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Expand); |
| 46 setOperationAction(ISD::MUL, MVT::v2i32, Expand); | |
| 47 setOperationAction(ISD::MUL, MVT::v4i32, Expand); | |
| 48 setOperationAction(ISD::OR, MVT::v4i32, Expand); | 46 setOperationAction(ISD::OR, MVT::v4i32, Expand); |
| 49 setOperationAction(ISD::OR, MVT::v2i32, Expand); | 47 setOperationAction(ISD::OR, MVT::v2i32, Expand); |
| 50 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Expand); | 48 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Expand); |
| 51 setOperationAction(ISD::SHL, MVT::v4i32, Expand); | 49 setOperationAction(ISD::SHL, MVT::v4i32, Expand); |
| 52 setOperationAction(ISD::SHL, MVT::v2i32, Expand); | 50 setOperationAction(ISD::SHL, MVT::v2i32, Expand); |
| 53 setOperationAction(ISD::SRL, MVT::v4i32, Expand); | 51 setOperationAction(ISD::SRL, MVT::v4i32, Expand); |
| 54 setOperationAction(ISD::SRL, MVT::v2i32, Expand); | 52 setOperationAction(ISD::SRL, MVT::v2i32, Expand); |
| 55 setOperationAction(ISD::SRA, MVT::v4i32, Expand); | |
| 56 setOperationAction(ISD::SRA, MVT::v2i32, Expand); | |
| 57 setOperationAction(ISD::SUB, MVT::v4i32, Expand); | |
| 58 setOperationAction(ISD::SUB, MVT::v2i32, Expand); | |
| 59 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Expand); | 53 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Expand); |
| 60 setOperationAction(ISD::UDIV, MVT::v4i32, Expand); | 54 setOperationAction(ISD::UDIV, MVT::v4i32, Expand); |
| 61 setOperationAction(ISD::UREM, MVT::v4i32, Expand); | 55 setOperationAction(ISD::UREM, MVT::v4i32, Expand); |
| 62 setOperationAction(ISD::SETCC, MVT::v4i32, Expand); | 56 setOperationAction(ISD::SETCC, MVT::v4i32, Expand); |
| 63 setOperationAction(ISD::XOR, MVT::v4i32, Expand); | 57 setOperationAction(ISD::XOR, MVT::v4i32, Expand); |
| 64 setOperationAction(ISD::XOR, MVT::v2i32, Expand); | 58 setOperationAction(ISD::XOR, MVT::v2i32, Expand); |
| 65 | 59 |
| 66 setOperationAction(ISD::BR_CC, MVT::i32, Expand); | 60 setOperationAction(ISD::BR_CC, MVT::i32, Expand); |
| 67 setOperationAction(ISD::BR_CC, MVT::f32, Expand); | 61 setOperationAction(ISD::BR_CC, MVT::f32, Expand); |
| 68 | 62 |
| 69 setOperationAction(ISD::FSUB, MVT::f32, Expand); | 63 setOperationAction(ISD::FSUB, MVT::f32, Expand); |
| 70 | 64 |
| 71 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom); | 65 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom); |
| 72 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); | 66 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); |
| 73 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i1, Custom); | 67 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i1, Custom); |
| 74 | 68 |
| 75 setOperationAction(ISD::ROTL, MVT::i32, Custom); | 69 setOperationAction(ISD::ROTL, MVT::i32, Custom); |
| 76 | 70 |
| 77 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); | 71 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); |
| 78 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); | 72 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); |
| 79 | 73 |
| 80 setOperationAction(ISD::SETCC, MVT::i32, Expand); | 74 setOperationAction(ISD::SETCC, MVT::i32, Expand); |
| 81 setOperationAction(ISD::SETCC, MVT::f32, Expand); | 75 setOperationAction(ISD::SETCC, MVT::f32, Expand); |
| 82 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Custom); | 76 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Custom); |
| 83 | 77 |
| 84 setOperationAction(ISD::SELECT, MVT::i32, Custom); | 78 setOperationAction(ISD::SELECT, MVT::i32, Custom); |
| 85 setOperationAction(ISD::SELECT, MVT::f32, Custom); | 79 setOperationAction(ISD::SELECT, MVT::f32, Custom); |
| 86 | 80 |
| 87 setOperationAction(ISD::VSELECT, MVT::v4i32, Expand); | |
| 88 setOperationAction(ISD::VSELECT, MVT::v2i32, Expand); | |
| 89 | |
| 90 // Legalize loads and stores to the private address space. | 81 // Legalize loads and stores to the private address space. |
| 91 setOperationAction(ISD::LOAD, MVT::i32, Custom); | 82 setOperationAction(ISD::LOAD, MVT::i32, Custom); |
| 92 setOperationAction(ISD::LOAD, MVT::v2i32, Custom); | 83 setOperationAction(ISD::LOAD, MVT::v2i32, Custom); |
| 93 setOperationAction(ISD::LOAD, MVT::v4i32, Custom); | 84 setOperationAction(ISD::LOAD, MVT::v4i32, Custom); |
| 94 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom); | 85 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom); |
| 95 setLoadExtAction(ISD::EXTLOAD, MVT::i8, Custom); | 86 setLoadExtAction(ISD::EXTLOAD, MVT::i8, Custom); |
| 96 setLoadExtAction(ISD::ZEXTLOAD, MVT::i8, Custom); | 87 setLoadExtAction(ISD::ZEXTLOAD, MVT::i8, Custom); |
| 97 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i8, Custom); | 88 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i8, Custom); |
| 98 setOperationAction(ISD::STORE, MVT::i8, Custom); | 89 setOperationAction(ISD::STORE, MVT::i8, Custom); |
| 99 setOperationAction(ISD::STORE, MVT::i32, Custom); | 90 setOperationAction(ISD::STORE, MVT::i32, Custom); |
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| 1115 NewBldVec[i] = Arg.getOperand(i); | 1106 NewBldVec[i] = Arg.getOperand(i); |
| 1116 } | 1107 } |
| 1117 } | 1108 } |
| 1118 DebugLoc DL = N->getDebugLoc(); | 1109 DebugLoc DL = N->getDebugLoc(); |
| 1119 NewArgs[1] = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4f32, NewBldVec, 4); | 1110 NewArgs[1] = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4f32, NewBldVec, 4); |
| 1120 return DAG.getNode(AMDGPUISD::EXPORT, DL, N->getVTList(), NewArgs, 8); | 1111 return DAG.getNode(AMDGPUISD::EXPORT, DL, N->getVTList(), NewArgs, 8); |
| 1121 } | 1112 } |
| 1122 } | 1113 } |
| 1123 return SDValue(); | 1114 return SDValue(); |
| 1124 } | 1115 } |
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