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| 1 //===-- AMDGPUMCTargetDesc.h - AMDGPU Target Descriptions -----*- C++ -*-===// | 1 //===-- AMDGPUMCTargetDesc.h - AMDGPU Target Descriptions -----*- C++ -*-===// |
| 2 // | 2 // |
| 3 // The LLVM Compiler Infrastructure | 3 // The LLVM Compiler Infrastructure |
| 4 // | 4 // |
| 5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
| 6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
| 7 // | 7 // |
| 8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
| 9 // | 9 // |
| 10 /// \file | 10 /// \file |
| (...skipping 15 matching lines...) Expand all Loading... |
| 26 class MCObjectWriter; | 26 class MCObjectWriter; |
| 27 class MCRegisterInfo; | 27 class MCRegisterInfo; |
| 28 class MCSubtargetInfo; | 28 class MCSubtargetInfo; |
| 29 class Target; | 29 class Target; |
| 30 class raw_ostream; | 30 class raw_ostream; |
| 31 | 31 |
| 32 extern Target TheAMDGPUTarget; | 32 extern Target TheAMDGPUTarget; |
| 33 | 33 |
| 34 MCCodeEmitter *createR600MCCodeEmitter(const MCInstrInfo &MCII, | 34 MCCodeEmitter *createR600MCCodeEmitter(const MCInstrInfo &MCII, |
| 35 const MCRegisterInfo &MRI, | 35 const MCRegisterInfo &MRI, |
| 36 const MCSubtargetInfo &STI); | 36 const MCSubtargetInfo &STI, |
| 37 MCContext &Ctx); |
| 37 | 38 |
| 38 MCCodeEmitter *createSIMCCodeEmitter(const MCInstrInfo &MCII, | 39 MCCodeEmitter *createSIMCCodeEmitter(const MCInstrInfo &MCII, |
| 39 const MCRegisterInfo &MRI, | 40 const MCRegisterInfo &MRI, |
| 40 const MCSubtargetInfo &STI, | 41 const MCSubtargetInfo &STI, |
| 41 MCContext &Ctx); | 42 MCContext &Ctx); |
| 42 | 43 |
| 43 MCAsmBackend *createAMDGPUAsmBackend(const Target &T, StringRef TT, | 44 MCAsmBackend *createAMDGPUAsmBackend(const Target &T, StringRef TT, |
| 44 StringRef CPU); | 45 StringRef CPU); |
| 45 | 46 |
| 46 MCObjectWriter *createAMDGPUELFObjectWriter(raw_ostream &OS); | 47 MCObjectWriter *createAMDGPUELFObjectWriter(raw_ostream &OS); |
| 47 } // End llvm namespace | 48 } // End llvm namespace |
| 48 | 49 |
| 49 #define GET_REGINFO_ENUM | 50 #define GET_REGINFO_ENUM |
| 50 #include "AMDGPUGenRegisterInfo.inc" | 51 #include "AMDGPUGenRegisterInfo.inc" |
| 51 | 52 |
| 52 #define GET_INSTRINFO_ENUM | 53 #define GET_INSTRINFO_ENUM |
| 53 #include "AMDGPUGenInstrInfo.inc" | 54 #include "AMDGPUGenInstrInfo.inc" |
| 54 | 55 |
| 55 #define GET_SUBTARGETINFO_ENUM | 56 #define GET_SUBTARGETINFO_ENUM |
| 56 #include "AMDGPUGenSubtargetInfo.inc" | 57 #include "AMDGPUGenSubtargetInfo.inc" |
| 57 | 58 |
| 58 #endif // AMDGPUMCTARGETDESC_H | 59 #endif // AMDGPUMCTARGETDESC_H |
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