Prep for merging 3.4: Undo changes from 3.3 branch

lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp

 //===-- NVPTXISelDAGToDAG.cpp - A dag to dag inst selector for NVPTX ------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file defines an instruction selector for the NVPTX target.
@@ skipping 24 matching lines @@
                  cl::desc("NVPTX Specific: FMA contraction (0: don't do it"
                           " 1: do it  2: do it aggressively"),
                  cl::init(2));
 
 static cl::opt<int> UsePrecDivF32(
     "nvptx-prec-divf32", cl::ZeroOrMore,
     cl::desc("NVPTX Specifies: 0 use div.approx, 1 use div.full, 2 use"
              " IEEE Compliant F32 div.rnd if avaiable."),
     cl::init(2));
 
-static cl::opt<bool>
-UsePrecSqrtF32("nvptx-prec-sqrtf32",
-          cl::desc("NVPTX Specific: 0 use sqrt.approx, 1 use sqrt.rn."),
-          cl::init(true));
-
 /// createNVPTXISelDag - This pass converts a legalized DAG into a
 /// NVPTX-specific DAG, ready for instruction scheduling.
 FunctionPass *llvm::createNVPTXISelDag(NVPTXTargetMachine &TM,
                                        llvm::CodeGenOpt::Level OptLevel) {
   return new NVPTXDAGToDAGISel(TM, OptLevel);
 }
 
 NVPTXDAGToDAGISel::NVPTXDAGToDAGISel(NVPTXTargetMachine &tm,
                                      CodeGenOpt::Level OptLevel)
     : SelectionDAGISel(tm, OptLevel),
@@ skipping 12 matching lines @@
       (OptLevel > 0) && Subtarget.hasFMAF64() && (FMAContractLevel == 2);
 
   allowFMA = (FMAContractLevel >= 1) || UseFMADInstruction;
 
   UseF32FTZ = false;
 
   doMulWide = (OptLevel > 0);
 
   // Decide how to translate f32 div
   do_DIVF32_PREC = UsePrecDivF32;
-  // Decide how to translate f32 sqrt
-  do_SQRTF32_PREC = UsePrecSqrtF32;
   // sm less than sm_20 does not support div.rnd. Use div.full.
   if (do_DIVF32_PREC == 2 && !Subtarget.reqPTX20())
     do_DIVF32_PREC = 1;
 
 }
 
 /// Select - Select instructions not customized! Used for
 /// expanded, promoted and normal instructions.
 SDNode *NVPTXDAGToDAGISel::Select(SDNode *N) {
 
@@ skipping 1637 matching lines @@
 
   if (N.getOpcode() == ISD::UNDEF)
     Retval = CurDAG->getTargetConstant(0, MVT::i8);
   else {
     ConstantSDNode *cn = cast<ConstantSDNode>(N.getNode());
     unsigned retval = cn->getZExtValue();
     Retval = CurDAG->getTargetConstant(retval, MVT::i8);
   }
   return true;
 }