MIPS64: Replace JR/JALR with JIC/JIALC for r6.

src/full-codegen/mips64/full-codegen-mips64.cc

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #if V8_TARGET_ARCH_MIPS64
 
 // Note on Mips implementation:
 //
 // The result_register() for mips is the 'v0' register, which is defined
 // by the ABI to contain function return values. However, the first
@@ skipping 4044 matching lines @@
 }
 
 #undef __
 
 
 void BackEdgeTable::PatchAt(Code* unoptimized_code,
                             Address pc,
                             BackEdgeState target_state,
                             Code* replacement_code) {
   static const int kInstrSize = Assembler::kInstrSize;
-  Address branch_address = pc - 8 * kInstrSize;
+  Address branch_address;
+  if (kArchVariant == kMips64r6) {
+    branch_address = pc - 7 * kInstrSize;
+  } else {
+    branch_address = pc - 8 * kInstrSize;
+  }

[balazs.kilvady, 2016/03/24 17:03:10]

Could you use the same constant-based solution here as on 32-bit part 2 CL? And
for the all of the other pc +/- <magic value> part. Do you plan to create a
separated 64 version of the ... part 2 CL?

[miran.karic, 2016/03/25 09:30:09]

Yes, I was planing to do that the same way as for mips32. When I finish testing
I will upload the CL. These are all the changes I plan to do, the rest of the
code uses j/jal in mips64 so I won't change it. 

   Isolate* isolate = unoptimized_code->GetIsolate();
   CodePatcher patcher(isolate, branch_address, 1);
 
   switch (target_state) {
     case INTERRUPT:
       // slt  at, a3, zero_reg (in case of count based interrupts)
       // beq  at, zero_reg, ok
       // lui  t9, <interrupt stub address> upper
       // ori  t9, <interrupt stub address> u-middle
       // dsll t9, t9, 16
       // ori  t9, <interrupt stub address> lower
       // jalr t9
       // nop
       // ok-label ----- pc_after points here
       patcher.masm()->slt(at, a3, zero_reg);
       break;
     case ON_STACK_REPLACEMENT:
       // addiu at, zero_reg, 1
       // beq  at, zero_reg, ok  ;; Not changed
       // lui  t9, <on-stack replacement address> upper
       // ori  t9, <on-stack replacement address> middle
       // dsll t9, t9, 16
       // ori  t9, <on-stack replacement address> lower
       // jalr t9  ;; Not changed
       // nop  ;; Not changed
       // ok-label ----- pc_after points here
       patcher.masm()->daddiu(at, zero_reg, 1);
       break;
   }
-  Address pc_immediate_load_address = pc - 6 * kInstrSize;
+  Address pc_immediate_load_address;
+  if (kArchVariant == kMips64r6) {
+    pc_immediate_load_address = pc - 5 * kInstrSize;
+  } else {
+    pc_immediate_load_address = pc - 6 * kInstrSize;
+  }
   // Replace the stack check address in the load-immediate (6-instr sequence)
   // with the entry address of the replacement code.
   Assembler::set_target_address_at(isolate, pc_immediate_load_address,
                                    replacement_code->entry());
 
   unoptimized_code->GetHeap()->incremental_marking()->RecordCodeTargetPatch(
       unoptimized_code, pc_immediate_load_address, replacement_code);
 }
 
 
 BackEdgeTable::BackEdgeState BackEdgeTable::GetBackEdgeState(
     Isolate* isolate,
     Code* unoptimized_code,
     Address pc) {
   static const int kInstrSize = Assembler::kInstrSize;
-  Address branch_address = pc - 8 * kInstrSize;
+  Address branch_address;
 #ifdef DEBUG
-  Address pc_immediate_load_address = pc - 6 * kInstrSize;
+  Address pc_immediate_load_address;
 #endif
+  if (kArchVariant == kMips64r6) {
+    branch_address = pc - 7 * kInstrSize;
+#ifdef DEBUG
+    pc_immediate_load_address = pc - 5 * kInstrSize;
+#endif
+    DCHECK(Assembler::IsBeq(Assembler::instr_at(pc - 6 * kInstrSize)));
+  } else {
+    branch_address = pc - 8 * kInstrSize;
+#ifdef DEBUG
+    pc_immediate_load_address = pc - 6 * kInstrSize;
+#endif
+    DCHECK(Assembler::IsBeq(Assembler::instr_at(pc - 7 * kInstrSize)));
+  }
 
-  DCHECK(Assembler::IsBeq(Assembler::instr_at(pc - 7 * kInstrSize)));
   if (!Assembler::IsAddImmediate(Assembler::instr_at(branch_address))) {
     DCHECK(reinterpret_cast<uint64_t>(
         Assembler::target_address_at(pc_immediate_load_address)) ==
            reinterpret_cast<uint64_t>(
                isolate->builtins()->InterruptCheck()->entry()));
     return INTERRUPT;
   }
 
   DCHECK(Assembler::IsAddImmediate(Assembler::instr_at(branch_address)));
 
   DCHECK(reinterpret_cast<uint64_t>(
              Assembler::target_address_at(pc_immediate_load_address)) ==
          reinterpret_cast<uint64_t>(
              isolate->builtins()->OnStackReplacement()->entry()));
   return ON_STACK_REPLACEMENT;
 }
 
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_TARGET_ARCH_MIPS64