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| 1 // Copyright 2012 the V8 project authors. All rights reserved. | 1 // Copyright 2012 the V8 project authors. All rights reserved. |
| 2 // Redistribution and use in source and binary forms, with or without | 2 // Redistribution and use in source and binary forms, with or without |
| 3 // modification, are permitted provided that the following conditions are | 3 // modification, are permitted provided that the following conditions are |
| 4 // met: | 4 // met: |
| 5 // | 5 // |
| 6 // * Redistributions of source code must retain the above copyright | 6 // * Redistributions of source code must retain the above copyright |
| 7 // notice, this list of conditions and the following disclaimer. | 7 // notice, this list of conditions and the following disclaimer. |
| 8 // * Redistributions in binary form must reproduce the above | 8 // * Redistributions in binary form must reproduce the above |
| 9 // copyright notice, this list of conditions and the following | 9 // copyright notice, this list of conditions and the following |
| 10 // disclaimer in the documentation and/or other materials provided | 10 // disclaimer in the documentation and/or other materials provided |
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| 215 // combinations are possible. | 215 // combinations are possible. |
| 216 | 216 |
| 217 if (source->IsRegister()) { | 217 if (source->IsRegister()) { |
| 218 Register source_register = cgen_->ToRegister(source); | 218 Register source_register = cgen_->ToRegister(source); |
| 219 if (destination->IsRegister()) { | 219 if (destination->IsRegister()) { |
| 220 __ mov(cgen_->ToRegister(destination), source_register); | 220 __ mov(cgen_->ToRegister(destination), source_register); |
| 221 } else { | 221 } else { |
| 222 ASSERT(destination->IsStackSlot()); | 222 ASSERT(destination->IsStackSlot()); |
| 223 __ sw(source_register, cgen_->ToMemOperand(destination)); | 223 __ sw(source_register, cgen_->ToMemOperand(destination)); |
| 224 } | 224 } |
| 225 | |
| 226 } else if (source->IsStackSlot()) { | 225 } else if (source->IsStackSlot()) { |
| 227 MemOperand source_operand = cgen_->ToMemOperand(source); | 226 MemOperand source_operand = cgen_->ToMemOperand(source); |
| 228 if (destination->IsRegister()) { | 227 if (destination->IsRegister()) { |
| 229 __ lw(cgen_->ToRegister(destination), source_operand); | 228 __ lw(cgen_->ToRegister(destination), source_operand); |
| 230 } else { | 229 } else { |
| 231 ASSERT(destination->IsStackSlot()); | 230 ASSERT(destination->IsStackSlot()); |
| 232 MemOperand destination_operand = cgen_->ToMemOperand(destination); | 231 MemOperand destination_operand = cgen_->ToMemOperand(destination); |
| 233 if (in_cycle_) { | 232 if (in_cycle_) { |
| 234 if (!destination_operand.OffsetIsInt16Encodable()) { | 233 if (!destination_operand.OffsetIsInt16Encodable()) { |
| 235 // 'at' is overwritten while saving the value to the destination. | 234 // 'at' is overwritten while saving the value to the destination. |
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| 252 LConstantOperand* constant_source = LConstantOperand::cast(source); | 251 LConstantOperand* constant_source = LConstantOperand::cast(source); |
| 253 if (destination->IsRegister()) { | 252 if (destination->IsRegister()) { |
| 254 Register dst = cgen_->ToRegister(destination); | 253 Register dst = cgen_->ToRegister(destination); |
| 255 if (cgen_->IsSmi(constant_source)) { | 254 if (cgen_->IsSmi(constant_source)) { |
| 256 __ li(dst, Operand(cgen_->ToSmi(constant_source))); | 255 __ li(dst, Operand(cgen_->ToSmi(constant_source))); |
| 257 } else if (cgen_->IsInteger32(constant_source)) { | 256 } else if (cgen_->IsInteger32(constant_source)) { |
| 258 __ li(dst, Operand(cgen_->ToInteger32(constant_source))); | 257 __ li(dst, Operand(cgen_->ToInteger32(constant_source))); |
| 259 } else { | 258 } else { |
| 260 __ LoadObject(dst, cgen_->ToHandle(constant_source)); | 259 __ LoadObject(dst, cgen_->ToHandle(constant_source)); |
| 261 } | 260 } |
| 261 } else if (source->IsDoubleRegister()) { |
| 262 DoubleRegister result = cgen_->ToDoubleRegister(destination); |
| 263 double v = cgen_->ToDouble(constant_source); |
| 264 __ Move(result, v); |
| 262 } else { | 265 } else { |
| 263 ASSERT(destination->IsStackSlot()); | 266 ASSERT(destination->IsStackSlot()); |
| 264 ASSERT(!in_cycle_); // Constant moves happen after all cycles are gone. | 267 ASSERT(!in_cycle_); // Constant moves happen after all cycles are gone. |
| 265 if (cgen_->IsSmi(constant_source)) { | 268 if (cgen_->IsSmi(constant_source)) { |
| 266 __ li(kLithiumScratchReg, Operand(cgen_->ToSmi(constant_source))); | 269 __ li(kLithiumScratchReg, Operand(cgen_->ToSmi(constant_source))); |
| 267 } else if (cgen_->IsInteger32(constant_source)) { | 270 } else if (cgen_->IsInteger32(constant_source)) { |
| 268 __ li(kLithiumScratchReg, | 271 __ li(kLithiumScratchReg, |
| 269 Operand(cgen_->ToInteger32(constant_source))); | 272 Operand(cgen_->ToInteger32(constant_source))); |
| 270 } else { | 273 } else { |
| 271 __ LoadObject(kLithiumScratchReg, | 274 __ LoadObject(kLithiumScratchReg, |
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| 311 UNREACHABLE(); | 314 UNREACHABLE(); |
| 312 } | 315 } |
| 313 | 316 |
| 314 moves_[index].Eliminate(); | 317 moves_[index].Eliminate(); |
| 315 } | 318 } |
| 316 | 319 |
| 317 | 320 |
| 318 #undef __ | 321 #undef __ |
| 319 | 322 |
| 320 } } // namespace v8::internal | 323 } } // namespace v8::internal |
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