Version 5.0.71.21: Merge arm64 CacheLineSizes revert

src/arm64/assembler-arm64.cc

Index: src/arm64/assembler-arm64.cc
diff --git a/src/arm64/assembler-arm64.cc b/src/arm64/assembler-arm64.cc
index d49c29fa244032c9316b1f70d09d5d9d6a7f5867..ea7a732f8a9146d270a515c0324a96afcd0f9ff4 100644
--- a/src/arm64/assembler-arm64.cc
+++ b/src/arm64/assembler-arm64.cc
@@ -58,9 +58,6 @@ void CpuFeatures::ProbeImpl(bool cross_compile) {
       cpu.part() <= base::CPU::NVIDIA_DENVER_V10) {
     supported_ |= 1u << COHERENT_CACHE;
   }
-
-  icache_line_size_ = cpu.icache_line_size();
-  dcache_line_size_ = cpu.dcache_line_size();
 }