MIPS: [wasm] Lowering of Int64Shl, Int64Shr, Int64Sar, Int64Add and Int64Sub.

src/compiler/mips/code-generator-mips.cc

Index: src/compiler/mips/code-generator-mips.cc
diff --git a/src/compiler/mips/code-generator-mips.cc b/src/compiler/mips/code-generator-mips.cc
index 26074af6275f76c43b0b8924235e6075f07776d6..915f215e2d580f9246e099cb2e2094b165317f4e 100644
--- a/src/compiler/mips/code-generator-mips.cc
+++ b/src/compiler/mips/code-generator-mips.cc
@@ -830,6 +830,36 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
         __ sra(i.OutputRegister(), i.InputRegister(0), imm);
       }
       break;
+    case kMipsShlPair: {
+      if (instr->InputAt(2)->IsRegister()) {
+        __ ShlPair(i.OutputRegister(0), i.OutputRegister(1), i.InputRegister(0),
+                   i.InputRegister(1), i.InputRegister(2));
+      } else {
+        uint32_t imm = i.InputOperand(2).immediate();
+        __ ShlPair(i.OutputRegister(0), i.OutputRegister(1), i.InputRegister(0),
+                   i.InputRegister(1), imm);
+      }
+    } break;
+    case kMipsShrPair: {
+      if (instr->InputAt(2)->IsRegister()) {
+        __ ShrPair(i.OutputRegister(0), i.OutputRegister(1), i.InputRegister(0),
+                   i.InputRegister(1), i.InputRegister(2));
+      } else {
+        uint32_t imm = i.InputOperand(2).immediate();
+        __ ShrPair(i.OutputRegister(0), i.OutputRegister(1), i.InputRegister(0),
+                   i.InputRegister(1), imm);
+      }
+    } break;
+    case kMipsSarPair: {
+      if (instr->InputAt(2)->IsRegister()) {
+        __ SarPair(i.OutputRegister(0), i.OutputRegister(1), i.InputRegister(0),
+                   i.InputRegister(1), i.InputRegister(2));
+      } else {
+        uint32_t imm = i.InputOperand(2).immediate();
+        __ SarPair(i.OutputRegister(0), i.OutputRegister(1), i.InputRegister(0),
+                   i.InputRegister(1), imm);
+      }
+    } break;
     case kMipsExt:
       __ Ext(i.OutputRegister(), i.InputRegister(0), i.InputInt8(1),
              i.InputInt8(2));
@@ -914,6 +944,32 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
     case kMipsCmpD:
       // Psuedo-instruction used for FP cmp/branch. No opcode emitted here.
       break;
+    case kMipsAddPair: {

[balazs.kilvady, 2016/03/30 11:52:52]

I would add AddPair and SubPair to MacroAssembler like at the previous shiftPair
ops. On ARM they don't need a MacroAssembler function as they have add(); adc()
pair.

[Marija Antic, 2016/03/30 14:21:09]

Done.

+      Label no_overflow;
+      // Add lower word
+      __ Addu(i.OutputRegister(0), i.InputRegister(0), i.InputRegister(2));
+      __ Addu(i.OutputRegister(1), i.InputRegister(1), i.InputRegister(3));
+      // Check for lower word overflow

[balazs.kilvady, 2016/03/30 11:52:52]

What about the AddBranchOvf() usage? You said earlier you are working on that. I
think if there are errors with AddBranchOvf then we have to fix that instruction
instead of avoid using it. In that case please let me know the details.

[akos.palfi.imgtec, 2016/03/30 12:00:33]

We discussed offline that the AddBranchOvf wrongly detects the overflow and I
suggested that we should land the CL without AddBranchOvf for now and we can
investigate that issue later.

[Marija Antic, 2016/03/30 13:16:20]

Issue 283 is opened for the problems with AddBranchOvf and SubBranchOvf.

On 2016/03/30 11:52:52, balazs.kilvady wrote:

+      __ Sltu(kScratchReg, i.OutputRegister(0), i.InputRegister(0));
+      __ Sltu(kScratchReg2, i.OutputRegister(0), i.InputRegister(2));
+      __ Or(kScratchReg, kScratchReg2, kScratchReg);
+      __ Branch(&no_overflow, eq, kScratchReg, Operand(zero_reg));
+      // Increment higher word if there was overflow
+      __ Addu(i.OutputRegister(1), i.OutputRegister(1), 0x1);
+      __ bind(&no_overflow);
+    } break;
+    case kMipsSubPair: {
+      Label no_overflow;
+      // Subtract lower word
+      __ Subu(i.OutputRegister(0), i.InputRegister(0), i.InputRegister(2));
+      __ Subu(i.OutputRegister(1), i.InputRegister(1), i.InputRegister(3));
+      // Check for lower word underflow
+      __ Sltu(kScratchReg, i.InputRegister(0), i.OutputRegister(0));

[ahaas, 2016/03/30 13:32:47]

I think this comparison is not sufficient. I think it would be better if you
compare i.InputRegister(0) with i.InputRegister(2) here.

[Marija Antic, 2016/03/30 14:21:09]

Done.

+      __ Branch(&no_overflow, eq, kScratchReg, Operand(zero_reg));
+      // Decrement higher word if there was underflow
+      __ Subu(i.OutputRegister(1), i.OutputRegister(1), 0x1);
+      __ bind(&no_overflow);
+    } break;
     case kMipsAddD:
       // TODO(plind): add special case: combine mult & add.
       __ add_d(i.OutputDoubleRegister(), i.InputDoubleRegister(0),