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Side by Side Diff: src/compiler/mips/instruction-codes-mips.h

Issue 1819383002: MIPS: [wasm] Lowering of Int64Shl, Int64Shr, Int64Sar, Int64Add and Int64Sub. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Enable all lowering tests Created 4 years, 8 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
7 7
8 namespace v8 { 8 namespace v8 {
9 namespace internal { 9 namespace internal {
10 namespace compiler { 10 namespace compiler {
(...skipping 15 matching lines...) Expand all
26 V(MipsAnd) \ 26 V(MipsAnd) \
27 V(MipsOr) \ 27 V(MipsOr) \
28 V(MipsNor) \ 28 V(MipsNor) \
29 V(MipsXor) \ 29 V(MipsXor) \
30 V(MipsClz) \ 30 V(MipsClz) \
31 V(MipsCtz) \ 31 V(MipsCtz) \
32 V(MipsPopcnt) \ 32 V(MipsPopcnt) \
33 V(MipsShl) \ 33 V(MipsShl) \
34 V(MipsShr) \ 34 V(MipsShr) \
35 V(MipsSar) \ 35 V(MipsSar) \
36 V(MipsShlPair) \
37 V(MipsShrPair) \
38 V(MipsSarPair) \
36 V(MipsExt) \ 39 V(MipsExt) \
37 V(MipsIns) \ 40 V(MipsIns) \
38 V(MipsRor) \ 41 V(MipsRor) \
39 V(MipsMov) \ 42 V(MipsMov) \
40 V(MipsTst) \ 43 V(MipsTst) \
41 V(MipsCmp) \ 44 V(MipsCmp) \
42 V(MipsCmpS) \ 45 V(MipsCmpS) \
43 V(MipsAddS) \ 46 V(MipsAddS) \
44 V(MipsSubS) \ 47 V(MipsSubS) \
45 V(MipsMulS) \ 48 V(MipsMulS) \
46 V(MipsDivS) \ 49 V(MipsDivS) \
47 V(MipsModS) \ 50 V(MipsModS) \
48 V(MipsAbsS) \ 51 V(MipsAbsS) \
49 V(MipsSqrtS) \ 52 V(MipsSqrtS) \
50 V(MipsMaxS) \ 53 V(MipsMaxS) \
51 V(MipsMinS) \ 54 V(MipsMinS) \
52 V(MipsCmpD) \ 55 V(MipsCmpD) \
53 V(MipsAddD) \ 56 V(MipsAddD) \
54 V(MipsSubD) \ 57 V(MipsSubD) \
55 V(MipsMulD) \ 58 V(MipsMulD) \
56 V(MipsDivD) \ 59 V(MipsDivD) \
57 V(MipsModD) \ 60 V(MipsModD) \
58 V(MipsAbsD) \ 61 V(MipsAbsD) \
59 V(MipsSqrtD) \ 62 V(MipsSqrtD) \
60 V(MipsMaxD) \ 63 V(MipsMaxD) \
61 V(MipsMinD) \ 64 V(MipsMinD) \
65 V(MipsAddPair) \
66 V(MipsSubPair) \
62 V(MipsFloat32RoundDown) \ 67 V(MipsFloat32RoundDown) \
63 V(MipsFloat32RoundTruncate) \ 68 V(MipsFloat32RoundTruncate) \
64 V(MipsFloat32RoundUp) \ 69 V(MipsFloat32RoundUp) \
65 V(MipsFloat32RoundTiesEven) \ 70 V(MipsFloat32RoundTiesEven) \
66 V(MipsFloat64RoundDown) \ 71 V(MipsFloat64RoundDown) \
67 V(MipsFloat64RoundTruncate) \ 72 V(MipsFloat64RoundTruncate) \
68 V(MipsFloat64RoundUp) \ 73 V(MipsFloat64RoundUp) \
69 V(MipsFloat64RoundTiesEven) \ 74 V(MipsFloat64RoundTiesEven) \
70 V(MipsCvtSD) \ 75 V(MipsCvtSD) \
71 V(MipsCvtDS) \ 76 V(MipsCvtDS) \
(...skipping 52 matching lines...) Expand 10 before | Expand all | Expand 10 after
124 #define TARGET_ADDRESSING_MODE_LIST(V) \ 129 #define TARGET_ADDRESSING_MODE_LIST(V) \
125 V(MRI) /* [%r0 + K] */ \ 130 V(MRI) /* [%r0 + K] */ \
126 V(MRR) /* [%r0 + %r1] */ 131 V(MRR) /* [%r0 + %r1] */
127 132
128 133
129 } // namespace compiler 134 } // namespace compiler
130 } // namespace internal 135 } // namespace internal
131 } // namespace v8 136 } // namespace v8
132 137
133 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 138 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
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