MIPS64: Fix test Cvt_s_uw_Trunc_uw_s.

MIPS64: Fix test Cvt_s_uw_Trunc_uw_s.

The higher word (bits 32 - 63) of FPU register is set on zero before
storing result.

TEST=cctest/test-macro-assembler-mips64/Cvt_s_uw_Trunc_uw_s
BUG=

Committed: https://crrev.com/a4e5d1541a10b4d4da8dc33250cb75df2c43154f
Cr-Commit-Position: refs/heads/master@{#34889}

[Ilija.Pavlovic1, 2016-03-18 11:30:57]

ilija.pavlovic@imgtec.com changed reviewers:
+ akos.palfi@imgtec.com, balazs.kilvady@imgtec.com, gergely.kis@imgtec.com,
ivica.bogosavljevic@imgtec.com, marija.antic@imgtec.com, miran.karic@imgtec.com

[Ilija.Pavlovic1, 2016-03-18 11:30:57]

PTAL.

The change is small. I would ask you to do a quick review.

Best regards
Ilija

[akos.palfi.imgtec, 2016-03-18 12:45:57]

LGTM

[Ilija.Pavlovic1, 2016-03-18 12:46:35]

The CQ bit was checked by ilija.pavlovic@imgtec.com

[commit-bot: I haz the power, 2016-03-18 12:46:43]

CQ is trying da patch. Follow status at
 https://chromium-cq-status.appspot.com/patch-status/1812193003/1
View timeline at
 https://chromium-cq-status.appspot.com/patch-timeline/1812193003/1

[commit-bot: I haz the power, 2016-03-18 13:21:32]

Committed patchset #1 (id:1)

[commit-bot: I haz the power, 2016-03-18 13:22:11]

Description was changed from

==========
MIPS64: Fix test Cvt_s_uw_Trunc_uw_s.

The higher word (bits 32 - 63) of FPU register is set on zero before
storing result.

TEST=cctest/test-macro-assembler-mips64/Cvt_s_uw_Trunc_uw_s
BUG=
==========

to

==========
MIPS64: Fix test Cvt_s_uw_Trunc_uw_s.

The higher word (bits 32 - 63) of FPU register is set on zero before
storing result.

TEST=cctest/test-macro-assembler-mips64/Cvt_s_uw_Trunc_uw_s
BUG=

Committed: https://crrev.com/a4e5d1541a10b4d4da8dc33250cb75df2c43154f
Cr-Commit-Position: refs/heads/master@{#34889}
==========

[commit-bot: I haz the power, 2016-03-18 13:22:13]

Patchset 1 (id:??) landed as
https://crrev.com/a4e5d1541a10b4d4da8dc33250cb75df2c43154f
Cr-Commit-Position: refs/heads/master@{#34889}