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1 // Copyright 2014 the V8 project authors. All rights reserved. | 1 // Copyright 2014 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #include "src/compiler/raw-machine-assembler.h" | 5 #include "src/compiler/raw-machine-assembler.h" |
6 | 6 |
7 #include "src/code-factory.h" | 7 #include "src/code-factory.h" |
8 #include "src/compiler/node-properties.h" | 8 #include "src/compiler/node-properties.h" |
9 #include "src/compiler/pipeline.h" | 9 #include "src/compiler/pipeline.h" |
10 #include "src/compiler/scheduler.h" | 10 #include "src/compiler/scheduler.h" |
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32 parameters_[i] = | 32 parameters_[i] = |
33 AddNode(common()->Parameter(static_cast<int>(i)), graph->start()); | 33 AddNode(common()->Parameter(static_cast<int>(i)), graph->start()); |
34 } | 34 } |
35 graph->SetEnd(graph->NewNode(common_.End(0))); | 35 graph->SetEnd(graph->NewNode(common_.End(0))); |
36 } | 36 } |
37 | 37 |
38 | 38 |
39 Schedule* RawMachineAssembler::Export() { | 39 Schedule* RawMachineAssembler::Export() { |
40 // Compute the correct codegen order. | 40 // Compute the correct codegen order. |
41 DCHECK(schedule_->rpo_order()->empty()); | 41 DCHECK(schedule_->rpo_order()->empty()); |
| 42 OFStream os(stdout); |
| 43 if (FLAG_trace_turbo_scheduler) { |
| 44 PrintF("--- RAW SCHEDULE -------------------------------------------\n"); |
| 45 os << *schedule_; |
| 46 } |
| 47 schedule_->EnsureSplitEdgeForm(); |
| 48 schedule_->PropagateDeferredMark(); |
| 49 if (FLAG_trace_turbo_scheduler) { |
| 50 PrintF("--- EDGE SPLIT AND PROPAGATED DEFERRED SCHEDULE ------------\n"); |
| 51 os << *schedule_; |
| 52 } |
42 Scheduler::ComputeSpecialRPO(zone(), schedule_); | 53 Scheduler::ComputeSpecialRPO(zone(), schedule_); |
43 // Invalidate RawMachineAssembler. | 54 // Invalidate RawMachineAssembler. |
44 Schedule* schedule = schedule_; | 55 Schedule* schedule = schedule_; |
45 schedule_ = nullptr; | 56 schedule_ = nullptr; |
46 return schedule; | 57 return schedule; |
47 } | 58 } |
48 | 59 |
49 | 60 |
50 Node* RawMachineAssembler::Parameter(size_t index) { | 61 Node* RawMachineAssembler::Parameter(size_t index) { |
51 DCHECK(index < parameter_count()); | 62 DCHECK(index < parameter_count()); |
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72 void RawMachineAssembler::Switch(Node* index, RawMachineLabel* default_label, | 83 void RawMachineAssembler::Switch(Node* index, RawMachineLabel* default_label, |
73 int32_t* case_values, | 84 int32_t* case_values, |
74 RawMachineLabel** case_labels, | 85 RawMachineLabel** case_labels, |
75 size_t case_count) { | 86 size_t case_count) { |
76 DCHECK_NE(schedule()->end(), current_block_); | 87 DCHECK_NE(schedule()->end(), current_block_); |
77 size_t succ_count = case_count + 1; | 88 size_t succ_count = case_count + 1; |
78 Node* switch_node = AddNode(common()->Switch(succ_count), index); | 89 Node* switch_node = AddNode(common()->Switch(succ_count), index); |
79 BasicBlock** succ_blocks = zone()->NewArray<BasicBlock*>(succ_count); | 90 BasicBlock** succ_blocks = zone()->NewArray<BasicBlock*>(succ_count); |
80 for (size_t index = 0; index < case_count; ++index) { | 91 for (size_t index = 0; index < case_count; ++index) { |
81 int32_t case_value = case_values[index]; | 92 int32_t case_value = case_values[index]; |
82 BasicBlock* case_block = Use(case_labels[index]); | 93 BasicBlock* case_block = schedule()->NewBasicBlock(); |
83 Node* case_node = | 94 Node* case_node = |
84 graph()->NewNode(common()->IfValue(case_value), switch_node); | 95 graph()->NewNode(common()->IfValue(case_value), switch_node); |
85 schedule()->AddNode(case_block, case_node); | 96 schedule()->AddNode(case_block, case_node); |
| 97 schedule()->AddGoto(case_block, Use(case_labels[index])); |
86 succ_blocks[index] = case_block; | 98 succ_blocks[index] = case_block; |
87 } | 99 } |
88 BasicBlock* default_block = Use(default_label); | 100 BasicBlock* default_block = schedule()->NewBasicBlock(); |
89 Node* default_node = graph()->NewNode(common()->IfDefault(), switch_node); | 101 Node* default_node = graph()->NewNode(common()->IfDefault(), switch_node); |
90 schedule()->AddNode(default_block, default_node); | 102 schedule()->AddNode(default_block, default_node); |
| 103 schedule()->AddGoto(default_block, Use(default_label)); |
91 succ_blocks[case_count] = default_block; | 104 succ_blocks[case_count] = default_block; |
92 schedule()->AddSwitch(CurrentBlock(), switch_node, succ_blocks, succ_count); | 105 schedule()->AddSwitch(CurrentBlock(), switch_node, succ_blocks, succ_count); |
93 current_block_ = nullptr; | 106 current_block_ = nullptr; |
94 } | 107 } |
95 | 108 |
96 | 109 |
97 void RawMachineAssembler::Return(Node* value) { | 110 void RawMachineAssembler::Return(Node* value) { |
98 Node* ret = MakeNode(common()->Return(), 1, &value); | 111 Node* ret = MakeNode(common()->Return(), 1, &value); |
99 NodeProperties::MergeControlToEnd(graph(), common(), ret); | 112 NodeProperties::MergeControlToEnd(graph(), common(), ret); |
100 schedule()->AddReturn(CurrentBlock(), ret); | 113 schedule()->AddReturn(CurrentBlock(), ret); |
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479 // The raw machine assembler nodes do not have effect and control inputs, | 492 // The raw machine assembler nodes do not have effect and control inputs, |
480 // so we disable checking input counts here. | 493 // so we disable checking input counts here. |
481 return graph()->NewNodeUnchecked(op, input_count, inputs); | 494 return graph()->NewNodeUnchecked(op, input_count, inputs); |
482 } | 495 } |
483 | 496 |
484 RawMachineLabel::~RawMachineLabel() { DCHECK(bound_ || !used_); } | 497 RawMachineLabel::~RawMachineLabel() { DCHECK(bound_ || !used_); } |
485 | 498 |
486 } // namespace compiler | 499 } // namespace compiler |
487 } // namespace internal | 500 } // namespace internal |
488 } // namespace v8 | 501 } // namespace v8 |
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