Index: src/compiler/pipeline.cc |
diff --git a/src/compiler/pipeline.cc b/src/compiler/pipeline.cc |
index 802024e5644f6d2892ac73444eb9b08cbc21c6d3..6129526553cd6dd20e524c6fd7b73ac70af268f0 100644 |
--- a/src/compiler/pipeline.cc |
+++ b/src/compiler/pipeline.cc |
@@ -267,13 +267,16 @@ class PipelineData { |
register_allocation_data_ = nullptr; |
} |
- void InitializeInstructionSequence() { |
+ void InitializeInstructionSequence(const CallDescriptor* descriptor) { |
DCHECK(sequence_ == nullptr); |
InstructionBlocks* instruction_blocks = |
InstructionSequence::InstructionBlocksFor(instruction_zone(), |
schedule()); |
sequence_ = new (instruction_zone()) InstructionSequence( |
info()->isolate(), instruction_zone(), instruction_blocks); |
+ if (descriptor && descriptor->RequiresFrameAsIncoming()) { |
+ sequence_->instruction_blocks()[0]->mark_needs_frame(); |
+ } |
} |
void InitializeFrameData(CallDescriptor* descriptor) { |
@@ -1336,7 +1339,7 @@ Handle<Code> Pipeline::ScheduleAndGenerateCode( |
data->schedule()); |
} |
- data->InitializeInstructionSequence(); |
+ data->InitializeInstructionSequence(call_descriptor); |
data->InitializeFrameData(call_descriptor); |
// Select and schedule instructions covering the scheduled graph. |
@@ -1485,12 +1488,6 @@ void Pipeline::AllocateRegisters(const RegisterConfiguration* config, |
Run<MergeSplintersPhase>(); |
} |
- // We plan to enable frame elision only for stubs and bytecode handlers. |
- if (FLAG_turbo_frame_elision && info()->IsStub()) { |
- Run<LocateSpillSlotsPhase>(); |
- Run<FrameElisionPhase>(); |
- } |
- |
Run<AssignSpillSlotsPhase>(); |
Run<CommitAssignmentPhase>(); |
@@ -1501,6 +1498,9 @@ void Pipeline::AllocateRegisters(const RegisterConfiguration* config, |
Run<OptimizeMovesPhase>(); |
} |
+ Run<LocateSpillSlotsPhase>(); |
+ Run<FrameElisionPhase>(); |
+ |
if (FLAG_trace_turbo_graph) { |
OFStream os(stdout); |
PrintableInstructionSequence printable = {config, data->sequence()}; |