MIPS: Replace JR/JALR with JIC/JIALC for r6 part 2

src/mips/assembler-mips.h

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 510 matching lines @@
   static const int kSpecialTargetSize = 0;
 
   // Number of consecutive instructions used to store 32bit constant. This
   // constant is used in RelocInfo::target_address_address() function to tell
   // serializer address of the instruction that follows LUI/ORI instruction
   // pair.
   static const int kInstructionsFor32BitConstant = 2;
 
   // Distance between the instruction referring to the address of the call
   // target and the return address.
+#ifdef _MIPS_ARCH_MIPS32R6
+  static const int kCallTargetAddressOffset = 3 * kInstrSize;
+#else
   static const int kCallTargetAddressOffset = 4 * kInstrSize;
+#endif
 
   // Distance between start of patched debug break slot and the emitted address
   // to jump to.
   static const int kPatchDebugBreakSlotAddressOffset = 4 * kInstrSize;
 
   // Difference between address of current opcode and value read from pc
   // register.
   static const int kPcLoadDelta = 4;
 
+#ifdef _MIPS_ARCH_MIPS32R6
+  static const int kDebugBreakSlotInstructions = 3;
+#else
   static const int kDebugBreakSlotInstructions = 4;
+#endif
   static const int kDebugBreakSlotLength =
       kDebugBreakSlotInstructions * kInstrSize;
 
 
   // ---------------------------------------------------------------------------
   // Code generation.
 
   // Insert the smallest number of nop instructions
   // possible to align the pc offset to a multiple
   // of m. m must be a power of 2 (>= 4).
@@ skipping 901 matching lines @@
  public:
   explicit EnsureSpace(Assembler* assembler) {
     assembler->CheckBuffer();
   }
 };
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_ARM_ASSEMBLER_MIPS_H_