MIPS: Replace JR/JALR with JIC/JIALC for r6 part 2

src/full-codegen/mips/full-codegen-mips.cc

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #if V8_TARGET_ARCH_MIPS
 
 // Note on Mips implementation:
 //
 // The result_register() for mips is the 'v0' register, which is defined
 // by the ABI to contain function return values. However, the first
@@ skipping 4129 matching lines @@
 }
 
 #undef __
 
 
 void BackEdgeTable::PatchAt(Code* unoptimized_code,
                             Address pc,
                             BackEdgeState target_state,
                             Code* replacement_code) {
   static const int kInstrSize = Assembler::kInstrSize;
-  Address branch_address = pc - 6 * kInstrSize;
+  Address branch_address;
+  if (IsMipsArchVariant(kMips32r6)) {
+    branch_address = pc - 5 * kInstrSize;

[ivica.bogosavljevic, 2016/03/21 15:30:48]

Instead of 5 and 6, is it possible to have here named constants which have
different values for different architectures? 5 and 6 or 3 or 4 doesn't mean
much.
In that case, there wouldn't be these branching depending on architecutre

[balazs.kilvady, 2016/03/24 12:12:47]

Could kCallTargetAddressOffset and other constants from assembler-mips.h be used
here? They are already arch-specific.

[miran.karic, 2016/03/24 15:34:01]

Done.

[miran.karic, 2016/03/24 15:34:01]

Done.

+  } else {
+    branch_address = pc - 6 * kInstrSize;
+  }
   Isolate* isolate = unoptimized_code->GetIsolate();
   CodePatcher patcher(isolate, branch_address, 1);
 
   switch (target_state) {
     case INTERRUPT:
       // slt at, a3, zero_reg (in case of count based interrupts)
       // beq at, zero_reg, ok
       // lui t9, <interrupt stub address> upper
       // ori t9, <interrupt stub address> lower
       // jalr t9
       // nop
       // ok-label ----- pc_after points here
       patcher.masm()->slt(at, a3, zero_reg);
       break;
     case ON_STACK_REPLACEMENT:
     case OSR_AFTER_STACK_CHECK:
       // addiu at, zero_reg, 1
       // beq at, zero_reg, ok  ;; Not changed
       // lui t9, <on-stack replacement address> upper
       // ori t9, <on-stack replacement address> lower
       // jalr t9  ;; Not changed
       // nop  ;; Not changed
       // ok-label ----- pc_after points here
       patcher.masm()->addiu(at, zero_reg, 1);
       break;
   }
-  Address pc_immediate_load_address = pc - 4 * kInstrSize;
+  Address pc_immediate_load_address;
+  if (IsMipsArchVariant(kMips32r6)) {
+    pc_immediate_load_address = pc - 3 * kInstrSize;

[ivica.bogosavljevic, 2016/03/21 15:30:48]

Same as above

[miran.karic, 2016/03/24 15:34:01]

Done.

+  } else {
+    pc_immediate_load_address = pc - 4 * kInstrSize;
+  }
   // Replace the stack check address in the load-immediate (lui/ori pair)
   // with the entry address of the replacement code.
   Assembler::set_target_address_at(isolate, pc_immediate_load_address,
                                    replacement_code->entry());
 
   unoptimized_code->GetHeap()->incremental_marking()->RecordCodeTargetPatch(
       unoptimized_code, pc_immediate_load_address, replacement_code);
 }
 
 
 BackEdgeTable::BackEdgeState BackEdgeTable::GetBackEdgeState(
     Isolate* isolate,
     Code* unoptimized_code,
     Address pc) {
   static const int kInstrSize = Assembler::kInstrSize;
-  Address branch_address = pc - 6 * kInstrSize;
-  Address pc_immediate_load_address = pc - 4 * kInstrSize;
+  Address branch_address;
+  Address pc_immediate_load_address;
+  if (IsMipsArchVariant(kMips32r6)) {
+    branch_address = pc - 5 * kInstrSize;
+    pc_immediate_load_address = pc - 3 * kInstrSize;
+    DCHECK(Assembler::IsBeq(Assembler::instr_at(pc - 4 * kInstrSize)));
+  } else {
+    branch_address = pc - 6 * kInstrSize;
+    pc_immediate_load_address = pc - 4 * kInstrSize;
+    DCHECK(Assembler::IsBeq(Assembler::instr_at(pc - 5 * kInstrSize)));
+  }
 
-  DCHECK(Assembler::IsBeq(Assembler::instr_at(pc - 5 * kInstrSize)));
   if (!Assembler::IsAddImmediate(Assembler::instr_at(branch_address))) {
     DCHECK(reinterpret_cast<uint32_t>(
         Assembler::target_address_at(pc_immediate_load_address)) ==
            reinterpret_cast<uint32_t>(
                isolate->builtins()->InterruptCheck()->entry()));
     return INTERRUPT;
   }
 
   DCHECK(Assembler::IsAddImmediate(Assembler::instr_at(branch_address)));
 
   if (reinterpret_cast<uint32_t>(
       Assembler::target_address_at(pc_immediate_load_address)) ==
           reinterpret_cast<uint32_t>(
               isolate->builtins()->OnStackReplacement()->entry())) {
     return ON_STACK_REPLACEMENT;
   }
 
   DCHECK(reinterpret_cast<uint32_t>(
       Assembler::target_address_at(pc_immediate_load_address)) ==
          reinterpret_cast<uint32_t>(
              isolate->builtins()->OsrAfterStackCheck()->entry()));
   return OSR_AFTER_STACK_CHECK;
 }
 
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_TARGET_ARCH_MIPS