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1 // Copyright 2014 the V8 project authors. All rights reserved. | 1 // Copyright 2014 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #include <assert.h> // For assert | 5 #include <assert.h> // For assert |
6 #include <limits.h> // For LONG_MIN, LONG_MAX. | 6 #include <limits.h> // For LONG_MIN, LONG_MAX. |
7 | 7 |
8 #if V8_TARGET_ARCH_S390 | 8 #if V8_TARGET_ARCH_S390 |
9 | 9 |
10 #include "src/base/bits.h" | 10 #include "src/base/bits.h" |
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4069 alg(dst, opnd); | 4069 alg(dst, opnd); |
4070 #else | 4070 #else |
4071 AddLogical(dst, opnd); | 4071 AddLogical(dst, opnd); |
4072 #endif | 4072 #endif |
4073 } | 4073 } |
4074 | 4074 |
4075 //---------------------------------------------------------------------------- | 4075 //---------------------------------------------------------------------------- |
4076 // Subtract Instructions | 4076 // Subtract Instructions |
4077 //---------------------------------------------------------------------------- | 4077 //---------------------------------------------------------------------------- |
4078 | 4078 |
| 4079 // Subtract Logical With Carry 32-bit (Register dst = Register src1 - Register |
| 4080 // src2) |
| 4081 void MacroAssembler::SubLogicalWithBorrow32(Register dst, Register src1, |
| 4082 Register src2) { |
| 4083 if (!dst.is(src2) && !dst.is(src1)) { |
| 4084 lr(dst, src1); |
| 4085 slbr(dst, src2); |
| 4086 } else if (!dst.is(src2)) { |
| 4087 // dst == src1 |
| 4088 DCHECK(dst.is(src1)); |
| 4089 slbr(dst, src2); |
| 4090 } else { |
| 4091 // dst == src2 |
| 4092 DCHECK(dst.is(src2)); |
| 4093 lr(r0, dst); |
| 4094 SubLogicalWithBorrow32(dst, src1, r0); |
| 4095 } |
| 4096 } |
| 4097 |
| 4098 // Subtract Logical 32-bit (Register dst = Register src1 - Register src2) |
| 4099 void MacroAssembler::SubLogical32(Register dst, Register src1, Register src2) { |
| 4100 if (!dst.is(src2) && !dst.is(src1)) { |
| 4101 lr(dst, src1); |
| 4102 slr(dst, src2); |
| 4103 } else if (!dst.is(src2)) { |
| 4104 // dst == src1 |
| 4105 DCHECK(dst.is(src1)); |
| 4106 slr(dst, src2); |
| 4107 } else { |
| 4108 // dst == src2 |
| 4109 DCHECK(dst.is(src2)); |
| 4110 lr(r0, dst); |
| 4111 SubLogical32(dst, src1, r0); |
| 4112 } |
| 4113 } |
| 4114 |
4079 // Subtract 32-bit (Register dst = Register dst - Immediate opnd) | 4115 // Subtract 32-bit (Register dst = Register dst - Immediate opnd) |
4080 void MacroAssembler::Sub32(Register dst, const Operand& imm) { | 4116 void MacroAssembler::Sub32(Register dst, const Operand& imm) { |
4081 Add32(dst, Operand(-(imm.imm_))); | 4117 Add32(dst, Operand(-(imm.imm_))); |
4082 } | 4118 } |
4083 | 4119 |
4084 // Subtract Pointer Size (Register dst = Register dst - Immediate opnd) | 4120 // Subtract Pointer Size (Register dst = Register dst - Immediate opnd) |
4085 void MacroAssembler::SubP(Register dst, const Operand& imm) { | 4121 void MacroAssembler::SubP(Register dst, const Operand& imm) { |
4086 AddP(dst, Operand(-(imm.imm_))); | 4122 AddP(dst, Operand(-(imm.imm_))); |
4087 } | 4123 } |
4088 | 4124 |
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5466 } | 5502 } |
5467 if (mag.shift > 0) ShiftRightArith(result, result, Operand(mag.shift)); | 5503 if (mag.shift > 0) ShiftRightArith(result, result, Operand(mag.shift)); |
5468 ExtractBit(r0, dividend, 31); | 5504 ExtractBit(r0, dividend, 31); |
5469 AddP(result, r0); | 5505 AddP(result, r0); |
5470 } | 5506 } |
5471 | 5507 |
5472 } // namespace internal | 5508 } // namespace internal |
5473 } // namespace v8 | 5509 } // namespace v8 |
5474 | 5510 |
5475 #endif // V8_TARGET_ARCH_S390 | 5511 #endif // V8_TARGET_ARCH_S390 |
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