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| 1 // Copyright 2014 the V8 project authors. All rights reserved. | 1 // Copyright 2014 the V8 project authors. All rights reserved. |
| 2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
| 3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
| 4 | 4 |
| 5 // A Disassembler object is used to disassemble a block of code instruction by | 5 // A Disassembler object is used to disassemble a block of code instruction by |
| 6 // instruction. The default implementation of the NameConverter object can be | 6 // instruction. The default implementation of the NameConverter object can be |
| 7 // overriden to modify register names or to do symbol lookup on addresses. | 7 // overriden to modify register names or to do symbol lookup on addresses. |
| 8 // | 8 // |
| 9 // The example below will disassemble a block of code and print it to stdout. | 9 // The example below will disassemble a block of code and print it to stdout. |
| 10 // | 10 // |
| (...skipping 763 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 774 break; | 774 break; |
| 775 case ALRK: | 775 case ALRK: |
| 776 Format(instr, "alrk\t'r5,'r6,'r3"); | 776 Format(instr, "alrk\t'r5,'r6,'r3"); |
| 777 break; | 777 break; |
| 778 case ALGRK: | 778 case ALGRK: |
| 779 Format(instr, "algrk\t'r5,'r6,'r3"); | 779 Format(instr, "algrk\t'r5,'r6,'r3"); |
| 780 break; | 780 break; |
| 781 case SLGR: | 781 case SLGR: |
| 782 Format(instr, "slgr\t'r5,'r6"); | 782 Format(instr, "slgr\t'r5,'r6"); |
| 783 break; | 783 break; |
| 784 case SLBR: |
| 785 Format(instr, "slbr\t'r5,'r6"); |
| 786 break; |
| 784 case DLR: | 787 case DLR: |
| 785 Format(instr, "dlr\t'r1,'r2"); | 788 Format(instr, "dlr\t'r1,'r2"); |
| 786 break; | 789 break; |
| 787 case DLGR: | 790 case DLGR: |
| 788 Format(instr, "dlgr\t'r5,'r6"); | 791 Format(instr, "dlgr\t'r5,'r6"); |
| 789 break; | 792 break; |
| 790 case SLRK: | 793 case SLRK: |
| 791 Format(instr, "slrk\t'r5,'r6,'r3"); | 794 Format(instr, "slrk\t'r5,'r6,'r3"); |
| 792 break; | 795 break; |
| 793 case SLGRK: | 796 case SLGRK: |
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| 1390 byte* prev_pc = pc; | 1393 byte* prev_pc = pc; |
| 1391 pc += d.InstructionDecode(buffer, pc); | 1394 pc += d.InstructionDecode(buffer, pc); |
| 1392 v8::internal::PrintF(f, "%p %08x %s\n", prev_pc, | 1395 v8::internal::PrintF(f, "%p %08x %s\n", prev_pc, |
| 1393 *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); | 1396 *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); |
| 1394 } | 1397 } |
| 1395 } | 1398 } |
| 1396 | 1399 |
| 1397 } // namespace disasm | 1400 } // namespace disasm |
| 1398 | 1401 |
| 1399 #endif // V8_TARGET_ARCH_S390 | 1402 #endif // V8_TARGET_ARCH_S390 |
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