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1 // Copyright 2014 the V8 project authors. All rights reserved. | 1 // Copyright 2014 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #include <assert.h> // For assert | 5 #include <assert.h> // For assert |
6 #include <limits.h> // For LONG_MIN, LONG_MAX. | 6 #include <limits.h> // For LONG_MIN, LONG_MAX. |
7 | 7 |
8 #if V8_TARGET_ARCH_S390 | 8 #if V8_TARGET_ARCH_S390 |
9 | 9 |
10 #include "src/base/bits.h" | 10 #include "src/base/bits.h" |
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3999 agsi(opnd, imm); | 3999 agsi(opnd, imm); |
4000 #else | 4000 #else |
4001 asi(opnd, imm); | 4001 asi(opnd, imm); |
4002 #endif | 4002 #endif |
4003 } | 4003 } |
4004 | 4004 |
4005 //---------------------------------------------------------------------------- | 4005 //---------------------------------------------------------------------------- |
4006 // Add Logical Instructions | 4006 // Add Logical Instructions |
4007 //---------------------------------------------------------------------------- | 4007 //---------------------------------------------------------------------------- |
4008 | 4008 |
| 4009 // Add Logical With Carry 32-bit (Register dst = Register src1 + Register src2) |
| 4010 void MacroAssembler::AddLogicalWithCarry32(Register dst, Register src1, |
| 4011 Register src2) { |
| 4012 if (!dst.is(src2) && !dst.is(src1)) { |
| 4013 lr(dst, src1); |
| 4014 alcr(dst, src2); |
| 4015 } else if (!dst.is(src2)) { |
| 4016 // dst == src1 |
| 4017 DCHECK(dst.is(src1)); |
| 4018 alcr(dst, src2); |
| 4019 } else { |
| 4020 // dst == src2 |
| 4021 DCHECK(dst.is(src2)); |
| 4022 alcr(dst, src1); |
| 4023 } |
| 4024 } |
| 4025 |
| 4026 // Add Logical 32-bit (Register dst = Register src1 + Register src2) |
| 4027 void MacroAssembler::AddLogical32(Register dst, Register src1, Register src2) { |
| 4028 if (!dst.is(src2) && !dst.is(src1)) { |
| 4029 lr(dst, src1); |
| 4030 alr(dst, src2); |
| 4031 } else if (!dst.is(src2)) { |
| 4032 // dst == src1 |
| 4033 DCHECK(dst.is(src1)); |
| 4034 alr(dst, src2); |
| 4035 } else { |
| 4036 // dst == src2 |
| 4037 DCHECK(dst.is(src2)); |
| 4038 alr(dst, src1); |
| 4039 } |
| 4040 } |
| 4041 |
4009 // Add Logical 32-bit (Register dst = Register dst + Immediate opnd) | 4042 // Add Logical 32-bit (Register dst = Register dst + Immediate opnd) |
4010 void MacroAssembler::AddLogical(Register dst, const Operand& imm) { | 4043 void MacroAssembler::AddLogical(Register dst, const Operand& imm) { |
4011 alfi(dst, imm); | 4044 alfi(dst, imm); |
4012 } | 4045 } |
4013 | 4046 |
4014 // Add Logical Pointer Size (Register dst = Register dst + Immediate opnd) | 4047 // Add Logical Pointer Size (Register dst = Register dst + Immediate opnd) |
4015 void MacroAssembler::AddLogicalP(Register dst, const Operand& imm) { | 4048 void MacroAssembler::AddLogicalP(Register dst, const Operand& imm) { |
4016 #ifdef V8_TARGET_ARCH_S390X | 4049 #ifdef V8_TARGET_ARCH_S390X |
4017 algfi(dst, imm); | 4050 algfi(dst, imm); |
4018 #else | 4051 #else |
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5433 } | 5466 } |
5434 if (mag.shift > 0) ShiftRightArith(result, result, Operand(mag.shift)); | 5467 if (mag.shift > 0) ShiftRightArith(result, result, Operand(mag.shift)); |
5435 ExtractBit(r0, dividend, 31); | 5468 ExtractBit(r0, dividend, 31); |
5436 AddP(result, r0); | 5469 AddP(result, r0); |
5437 } | 5470 } |
5438 | 5471 |
5439 } // namespace internal | 5472 } // namespace internal |
5440 } // namespace v8 | 5473 } // namespace v8 |
5441 | 5474 |
5442 #endif // V8_TARGET_ARCH_S390 | 5475 #endif // V8_TARGET_ARCH_S390 |
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