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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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1898 } | 1898 } |
1899 | 1899 |
1900 // Add Logical Immediate (32) | 1900 // Add Logical Immediate (32) |
1901 void Assembler::alfi(Register r1, const Operand& opnd) { | 1901 void Assembler::alfi(Register r1, const Operand& opnd) { |
1902 ril_form(ALFI, r1, opnd); | 1902 ril_form(ALFI, r1, opnd); |
1903 } | 1903 } |
1904 | 1904 |
1905 // Add Logical Register-Register (32) | 1905 // Add Logical Register-Register (32) |
1906 void Assembler::alr(Register r1, Register r2) { rr_form(ALR, r1, r2); } | 1906 void Assembler::alr(Register r1, Register r2) { rr_form(ALR, r1, r2); } |
1907 | 1907 |
| 1908 // Add Logical With Carry Register-Register (32) |
| 1909 void Assembler::alcr(Register r1, Register r2) { rre_form(ALCR, r1, r2); } |
| 1910 |
1908 // Add Logical Register-Register-Register (32) | 1911 // Add Logical Register-Register-Register (32) |
1909 void Assembler::alrk(Register r1, Register r2, Register r3) { | 1912 void Assembler::alrk(Register r1, Register r2, Register r3) { |
1910 rrf1_form(ALRK, r1, r2, r3); | 1913 rrf1_form(ALRK, r1, r2, r3); |
1911 } | 1914 } |
1912 | 1915 |
1913 // ------------------------------- | 1916 // ------------------------------- |
1914 // 64-bit Add Logical Instructions | 1917 // 64-bit Add Logical Instructions |
1915 // ------------------------------- | 1918 // ------------------------------- |
1916 // Add Logical Register-Storage (64) | 1919 // Add Logical Register-Storage (64) |
1917 void Assembler::alg(Register r1, const MemOperand& opnd) { | 1920 void Assembler::alg(Register r1, const MemOperand& opnd) { |
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3025 | 3028 |
3026 reloc_info_writer.Write(&rinfo); | 3029 reloc_info_writer.Write(&rinfo); |
3027 } | 3030 } |
3028 | 3031 |
3029 reloc_info_writer.Finish(); | 3032 reloc_info_writer.Finish(); |
3030 } | 3033 } |
3031 | 3034 |
3032 } // namespace internal | 3035 } // namespace internal |
3033 } // namespace v8 | 3036 } // namespace v8 |
3034 #endif // V8_TARGET_ARCH_S390 | 3037 #endif // V8_TARGET_ARCH_S390 |
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