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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions are | 5 // modification, are permitted provided that the following conditions are |
6 // met: | 6 // met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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222 #define xmm0 (static_cast<const XMMRegister&>(double_register_0)) | 222 #define xmm0 (static_cast<const XMMRegister&>(double_register_0)) |
223 #define xmm1 (static_cast<const XMMRegister&>(double_register_1)) | 223 #define xmm1 (static_cast<const XMMRegister&>(double_register_1)) |
224 #define xmm2 (static_cast<const XMMRegister&>(double_register_2)) | 224 #define xmm2 (static_cast<const XMMRegister&>(double_register_2)) |
225 #define xmm3 (static_cast<const XMMRegister&>(double_register_3)) | 225 #define xmm3 (static_cast<const XMMRegister&>(double_register_3)) |
226 #define xmm4 (static_cast<const XMMRegister&>(double_register_4)) | 226 #define xmm4 (static_cast<const XMMRegister&>(double_register_4)) |
227 #define xmm5 (static_cast<const XMMRegister&>(double_register_5)) | 227 #define xmm5 (static_cast<const XMMRegister&>(double_register_5)) |
228 #define xmm6 (static_cast<const XMMRegister&>(double_register_6)) | 228 #define xmm6 (static_cast<const XMMRegister&>(double_register_6)) |
229 #define xmm7 (static_cast<const XMMRegister&>(double_register_7)) | 229 #define xmm7 (static_cast<const XMMRegister&>(double_register_7)) |
230 | 230 |
231 | 231 |
232 struct X87TopOfStackRegister : IntelDoubleRegister { | 232 struct X87Register : IntelDoubleRegister { |
233 static const int kNumAllocatableRegisters = 1; | 233 static const int kNumAllocatableRegisters = 5; |
234 static const int kNumRegisters = 1; | 234 static const int kNumRegisters = 5; |
235 | 235 |
236 bool is(X87TopOfStackRegister reg) const { | 236 bool is(X87Register reg) const { |
237 return code_ == reg.code_; | 237 return code_ == reg.code_; |
238 } | 238 } |
239 | 239 |
240 static const char* AllocationIndexToString(int index) { | 240 static const char* AllocationIndexToString(int index) { |
241 ASSERT(index >= 0 && index < kNumAllocatableRegisters); | 241 ASSERT(index >= 0 && index < kNumAllocatableRegisters); |
242 const char* const names[] = { | 242 const char* const names[] = { |
243 "st0", | 243 "stX_0", "stX_1", "stX_2", "stX_3", "stX_4" |
244 }; | 244 }; |
245 return names[index]; | 245 return names[index]; |
246 } | 246 } |
247 | 247 |
248 static int ToAllocationIndex(X87TopOfStackRegister reg) { | 248 static X87Register FromAllocationIndex(int index) { |
249 ASSERT(reg.code() == 0); | 249 STATIC_ASSERT(sizeof(X87Register) == sizeof(IntelDoubleRegister)); |
250 return 0; | 250 ASSERT(index >= 0 && index < NumAllocatableRegisters()); |
| 251 X87Register result; |
| 252 result.code_ = index; |
| 253 return result; |
| 254 } |
| 255 |
| 256 static int ToAllocationIndex(X87Register reg) { |
| 257 return reg.code_; |
251 } | 258 } |
252 }; | 259 }; |
253 | 260 |
254 #define x87tos \ | 261 #define stX_0 static_cast<const X87Register&>(double_register_0) |
255 static_cast<const X87TopOfStackRegister&>(double_register_0) | 262 #define stX_1 static_cast<const X87Register&>(double_register_1) |
| 263 #define stX_2 static_cast<const X87Register&>(double_register_2) |
| 264 #define stX_3 static_cast<const X87Register&>(double_register_3) |
| 265 #define stX_4 static_cast<const X87Register&>(double_register_4) |
256 | 266 |
257 | 267 |
258 typedef IntelDoubleRegister DoubleRegister; | 268 typedef IntelDoubleRegister DoubleRegister; |
259 | 269 |
260 | 270 |
261 enum Condition { | 271 enum Condition { |
262 // any value < 0 is considered no_condition | 272 // any value < 0 is considered no_condition |
263 no_condition = -1, | 273 no_condition = -1, |
264 | 274 |
265 overflow = 0, | 275 overflow = 0, |
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940 void fsin(); | 950 void fsin(); |
941 void fptan(); | 951 void fptan(); |
942 void fyl2x(); | 952 void fyl2x(); |
943 void f2xm1(); | 953 void f2xm1(); |
944 void fscale(); | 954 void fscale(); |
945 void fninit(); | 955 void fninit(); |
946 | 956 |
947 void fadd(int i); | 957 void fadd(int i); |
948 void fsub(int i); | 958 void fsub(int i); |
949 void fmul(int i); | 959 void fmul(int i); |
| 960 void fmul_i(int i); |
950 void fdiv(int i); | 961 void fdiv(int i); |
951 | 962 |
952 void fisub_s(const Operand& adr); | 963 void fisub_s(const Operand& adr); |
953 | 964 |
954 void faddp(int i = 1); | 965 void faddp(int i = 1); |
955 void fsubp(int i = 1); | 966 void fsubp(int i = 1); |
956 void fsubrp(int i = 1); | 967 void fsubrp(int i = 1); |
957 void fmulp(int i = 1); | 968 void fmulp(int i = 1); |
958 void fdivp(int i = 1); | 969 void fdivp(int i = 1); |
959 void fprem(); | 970 void fprem(); |
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1219 private: | 1230 private: |
1220 Assembler* assembler_; | 1231 Assembler* assembler_; |
1221 #ifdef DEBUG | 1232 #ifdef DEBUG |
1222 int space_before_; | 1233 int space_before_; |
1223 #endif | 1234 #endif |
1224 }; | 1235 }; |
1225 | 1236 |
1226 } } // namespace v8::internal | 1237 } } // namespace v8::internal |
1227 | 1238 |
1228 #endif // V8_IA32_ASSEMBLER_IA32_H_ | 1239 #endif // V8_IA32_ASSEMBLER_IA32_H_ |
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