Subzero. Flags refactoring.

src/IceTargetLoweringARM32.cpp

 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 1014 matching lines @@
     createGotPtr();
   }
   genTargetHelperCalls();
   findMaxStackOutArgsSize();
 
   // Do not merge Alloca instructions, and lay out the stack.
   static constexpr bool SortAndCombineAllocas = true;
   Func->processAllocas(SortAndCombineAllocas);
   Func->dump("After Alloca processing");
 
-  if (!Ctx->getFlags().getPhiEdgeSplit()) {
+  if (!Ctx->getFlags().getEnablePhiEdgeSplit()) {
     // Lower Phi instructions.
     Func->placePhiLoads();
     if (Func->hasError())
       return;
     Func->placePhiStores();
     if (Func->hasError())
       return;
     Func->deletePhis();
     if (Func->hasError())
       return;
@@ skipping 47 matching lines @@
   // cleanup, to make the dump cleaner and more useful.
   Func->dump("After initial ARM32 codegen");
   Func->getVMetadata()->init(VMK_All);
   regAlloc(RAK_Global);
   if (Func->hasError())
     return;
 
   copyRegAllocFromInfWeightVariable64On32(Func->getVariables());
   Func->dump("After linear scan regalloc");
 
-  if (Ctx->getFlags().getPhiEdgeSplit()) {
+  if (Ctx->getFlags().getEnablePhiEdgeSplit()) {
     Func->advancedPhiLowering();
     Func->dump("After advanced Phi lowering");
   }
 
   ForbidTemporaryWithoutReg _(this);
 
   // Stack frame mapping.
   Func->genFrame();
   if (Func->hasError())
     return;
   Func->dump("After stack frame mapping");
 
   postLowerLegalization();
   if (Func->hasError())
     return;
   Func->dump("After postLowerLegalization");
 
   Func->contractEmptyNodes();
   Func->reorderNodes();
 
   // Branch optimization. This needs to be done just before code emission. In
   // particular, no transformations that insert or reorder CfgNodes should be
   // done after branch optimization. We go ahead and do it before nop insertion
   // to reduce the amount of work needed for searching for opportunities.
   Func->doBranchOpt();
   Func->dump("After branch optimization");
 
   // Nop insertion
-  if (Ctx->getFlags().shouldDoNopInsertion()) {
+  if (Ctx->getFlags().getShouldDoNopInsertion()) {
     Func->doNopInsertion();
   }
 }
 
 void TargetARM32::translateOm1() {
   TimerMarker T(TimerStack::TT_Om1, Func);
 
   // TODO(stichnot): share passes with other targets?
   if (SandboxingType == ST_Nonsfi) {
     createGotPtr();
@@ skipping 41 matching lines @@
   if (Func->hasError())
     return;
   Func->dump("After stack frame mapping");
 
   postLowerLegalization();
   if (Func->hasError())
     return;
   Func->dump("After postLowerLegalization");
 
   // Nop insertion
-  if (Ctx->getFlags().shouldDoNopInsertion()) {
+  if (Ctx->getFlags().getShouldDoNopInsertion()) {
     Func->doNopInsertion();
   }
 }
 
 uint32_t TargetARM32::getStackAlignment() const {
   return ARM32_STACK_ALIGNMENT_BYTES;
 }
 
 bool TargetARM32::doBranchOpt(Inst *I, const CfgNode *NextNode) {
   if (auto *Br = llvm::dyn_cast<InstARM32Br>(I)) {
@@ skipping 5591 matching lines @@
   static constexpr size_t MinimumAlignment = 4;
   SizeT Align = std::max(MinimumAlignment, typeAlignInBytes(Traits::IceType));
   assert((Align % 4) == 0 && "Constants should be aligned");
   Ostream &Str = Ctx->getStrEmit();
   ConstantList Pool = Ctx->getConstantPool(Traits::IceType);
 
   Str << "\t.section\t.rodata.cst" << Align << ",\"aM\",%progbits," << Align
       << "\n"
       << "\t.align\t" << Align << "\n";
 
-  if (Ctx->getFlags().shouldReorderPooledConstants()) {
+  if (Ctx->getFlags().getReorderPooledConstants()) {
     // TODO(jpp): add constant pooling.
     UnimplementedError(Ctx->getFlags());
   }
 
   for (Constant *C : Pool) {
     if (!C->getShouldBePooled()) {
       continue;
     }
 
     emitConstant<T>(Str, llvm::dyn_cast<typename Traits::ConstantType>(C));
@@ skipping 87 matching lines @@
   // However, for compatibility with current NaCl LLVM, don't claim that.
   Str << ".eabi_attribute 14, 3   @ Tag_ABI_PCS_R9_use: Not used\n";
 }
 
 SmallBitVector TargetARM32::TypeToRegisterSet[RegARM32::RCARM32_NUM];
 SmallBitVector TargetARM32::TypeToRegisterSetUnfiltered[RegARM32::RCARM32_NUM];
 SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM];
 
 } // end of namespace ARM32
 } // end of namespace Ice