Subzero. Flags refactoring.

src/IceTargetLowering.cpp

 //===- subzero/src/IceTargetLowering.cpp - Basic lowering implementation --===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// \brief Implements the skeleton of the TargetLowering class.
 ///
 /// Specifically this invokes the appropriate lowering method for a given
 /// instruction kind and driving global register allocation. It also implements
 /// the non-deleted instruction iteration in LoweringContext.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "IceTargetLowering.h"
 
 #include "IceBitVector.h"
 #include "IceCfg.h" // setError()
 #include "IceCfgNode.h"
 #include "IceGlobalContext.h"
 #include "IceGlobalInits.h"
 #include "IceInstVarIter.h"
 #include "IceOperand.h"
 #include "IceRegAlloc.h"
 
+#include <string>
+#include <vector>
+
 #define TARGET_LOWERING_CLASS_FOR(t) Target_##t
 
 // We prevent target-specific implementation details from leaking outside their
 // implementations by forbidding #include of target-specific header files
 // anywhere outside their own files. To create target-specific objects
 // (TargetLowering, TargetDataLowering, and TargetHeaderLowering) we use the
 // following named constructors. For reference, each target Foo needs to
 // implement the following named constructors and initializer:
 //
 // namespace Foo {
@@ skipping 132 matching lines @@
                                      SmallBitVector(NumRegs));
   std::vector<SmallBitVector> ExcludeSet(TypeToRegisterSetSize,
                                          SmallBitVector(NumRegs));
 
   std::unordered_map<IceString, RegNumT> RegNameToIndex;
   for (int32_t RegIndex = 0; RegIndex < NumRegs; ++RegIndex) {
     const auto RegNum = RegNumT::fromInt(RegIndex);
     RegNameToIndex[getRegName(RegNum)] = RegNum;
   }
 
-  ClFlags::StringVector BadRegNames;
+  std::vector<std::string> BadRegNames;
 
   // The processRegList function iterates across the RegNames vector.  Each
   // entry in the vector is a string of the form "<reg>" or "<class>:<reg>".
   // The register class and register number are computed, and the corresponding
   // bit is set in RegSet[][].  If "<class>:" is missing, then the bit is set
   // for all classes.
-  auto processRegList = [&](const ClFlags::StringVector &RegNames,
+  auto processRegList = [&](const std::vector<std::string> &RegNames,
                             std::vector<SmallBitVector> &RegSet) {
     for (const IceString &RegClassAndName : RegNames) {
       IceString RClass;
       IceString RName;
       splitToClassAndName(RegClassAndName, &RClass, &RName);
       if (!RegNameToIndex.count(RName)) {
         BadRegNames.push_back(RName);
         continue;
       }
       const int32_t RegIndex = RegNameToIndex.at(RName);
@@ skipping 267 matching lines @@
 void TargetLowering::regAlloc(RegAllocKind Kind) {
   TimerMarker T(TimerStack::TT_regAlloc, Func);
   LinearScan LinearScan(Func);
   RegSetMask RegInclude = RegSet_None;
   RegSetMask RegExclude = RegSet_None;
   RegInclude |= RegSet_CallerSave;
   RegInclude |= RegSet_CalleeSave;
   if (hasFramePointer())
     RegExclude |= RegSet_FramePointer;
   SmallBitVector RegMask = getRegisterSet(RegInclude, RegExclude);
-  bool Repeat = (Kind == RAK_Global && Ctx->getFlags().shouldRepeatRegAlloc());
+  bool Repeat = (Kind == RAK_Global && Ctx->getFlags().getRepeatRegAlloc());
   do {
     LinearScan.init(Kind);
-    LinearScan.scan(RegMask, Ctx->getFlags().shouldRandomizeRegAlloc());
+    LinearScan.scan(RegMask, Ctx->getFlags().getRandomizeRegisterAllocation());
     if (!LinearScan.hasEvictions())
       Repeat = false;
     Kind = RAK_SecondChance;
   } while (Repeat);
   // TODO(stichnot): Run the register allocator one more time to do stack slot
   // coalescing.  The idea would be to initialize the Unhandled list with the
   // set of Variables that have no register and a non-empty live range, and
   // model an infinite number of registers.  Maybe use the register aliasing
   // mechanism to get better packing of narrower slots.
 }
@@ skipping 390 matching lines @@
   case TARGET_LOWERING_CLASS_FOR(X):                                           \
     return ::X::createTargetHeaderLowering(Ctx);
 #include "SZTargets.def"
 #undef SUBZERO_TARGET
   }
 }
 
 TargetHeaderLowering::~TargetHeaderLowering() = default;
 
 } // end of namespace Ice