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| 1 // Copyright 2014 the V8 project authors. All rights reserved. | 1 // Copyright 2014 the V8 project authors. All rights reserved. |
| 2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
| 3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
| 4 | 4 |
| 5 // A Disassembler object is used to disassemble a block of code instruction by | 5 // A Disassembler object is used to disassemble a block of code instruction by |
| 6 // instruction. The default implementation of the NameConverter object can be | 6 // instruction. The default implementation of the NameConverter object can be |
| 7 // overriden to modify register names or to do symbol lookup on addresses. | 7 // overriden to modify register names or to do symbol lookup on addresses. |
| 8 // | 8 // |
| 9 // The example below will disassemble a block of code and print it to stdout. | 9 // The example below will disassemble a block of code and print it to stdout. |
| 10 // | 10 // |
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| 654 } | 654 } |
| 655 #endif | 655 #endif |
| 656 case SUBFCX: { | 656 case SUBFCX: { |
| 657 Format(instr, "subfc'. 'rt, 'ra, 'rb"); | 657 Format(instr, "subfc'. 'rt, 'ra, 'rb"); |
| 658 return; | 658 return; |
| 659 } | 659 } |
| 660 case ADDCX: { | 660 case ADDCX: { |
| 661 Format(instr, "addc'. 'rt, 'ra, 'rb"); | 661 Format(instr, "addc'. 'rt, 'ra, 'rb"); |
| 662 return; | 662 return; |
| 663 } | 663 } |
| 664 case ADDEX: { |
| 665 Format(instr, "adde'. 'rt, 'ra, 'rb"); |
| 666 return; |
| 667 } |
| 664 case CNTLZWX: { | 668 case CNTLZWX: { |
| 665 Format(instr, "cntlzw'. 'ra, 'rs"); | 669 Format(instr, "cntlzw'. 'ra, 'rs"); |
| 666 return; | 670 return; |
| 667 } | 671 } |
| 668 #if V8_TARGET_ARCH_PPC64 | 672 #if V8_TARGET_ARCH_PPC64 |
| 669 case CNTLZDX: { | 673 case CNTLZDX: { |
| 670 Format(instr, "cntlzd'. 'ra, 'rs"); | 674 Format(instr, "cntlzd'. 'ra, 'rs"); |
| 671 return; | 675 return; |
| 672 } | 676 } |
| 673 #endif | 677 #endif |
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| 1455 pc += d.InstructionDecode(buffer, pc); | 1459 pc += d.InstructionDecode(buffer, pc); |
| 1456 v8::internal::PrintF(f, "%p %08x %s\n", prev_pc, | 1460 v8::internal::PrintF(f, "%p %08x %s\n", prev_pc, |
| 1457 *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); | 1461 *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); |
| 1458 } | 1462 } |
| 1459 } | 1463 } |
| 1460 | 1464 |
| 1461 | 1465 |
| 1462 } // namespace disasm | 1466 } // namespace disasm |
| 1463 | 1467 |
| 1464 #endif // V8_TARGET_ARCH_PPC | 1468 #endif // V8_TARGET_ARCH_PPC |
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