Add X32 port into V8

src/x64/assembler-x64.cc

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 148 matching lines @@
 
 
 // -----------------------------------------------------------------------------
 // Implementation of RelocInfo
 
 // Patch the code at the current PC with a call to the target address.
 // Additional guard int3 instructions can be added if required.
 void RelocInfo::PatchCodeWithCall(Address target, int guard_bytes) {
   // Load register with immediate 64 and call through a register instructions
   // takes up 13 bytes and int3 takes up one byte.
+#ifndef V8_TARGET_ARCH_X32
   static const int kCallCodeSize = 13;
+#else
+  static const int kCallCodeSize = 9;
+#endif
   int code_size = kCallCodeSize + guard_bytes;
 
   // Create a code patcher.
   CodePatcher patcher(pc_, code_size);
 
   // Add a label for checking the size of the code used for returning.
 #ifdef DEBUG
   Label check_codesize;
   patcher.masm()->bind(&check_codesize);
 #endif
 
   // Patch the code.
+#ifndef V8_TARGET_ARCH_X32
   patcher.masm()->movq(r10, target, RelocInfo::NONE64);
+#else
+  patcher.masm()->movl(r10, target, RelocInfo::NONE32);
+#endif
   patcher.masm()->call(r10);
 
   // Check that the size of the code generated is as expected.
   ASSERT_EQ(kCallCodeSize,
             patcher.masm()->SizeOfCodeGeneratedSince(&check_codesize));
 
   // Add the requested number of int3 instructions after the call.
   for (int i = 0; i < guard_bytes; i++) {
     patcher.masm()->int3();
   }
@@ skipping 1173 matching lines @@
 void Assembler::leal(Register dst, const Operand& src) {
   EnsureSpace ensure_space(this);
   emit_optional_rex_32(dst, src);
   emit(0x8D);
   emit_operand(dst, src);
 }
 
 
 void Assembler::load_rax(void* value, RelocInfo::Mode mode) {
   EnsureSpace ensure_space(this);
+#ifndef V8_TARGET_ARCH_X32
   emit(0x48);  // REX.W
+#endif
   emit(0xA1);
+#ifndef V8_TARGET_ARCH_X32
   emitq(reinterpret_cast<uintptr_t>(value), mode);
+#else
+  // In 64-bit mode, need to zero extend the operand to 8 bytes.
+  // See 2.2.1.4 in Intel64 and IA32 Architectures Software
+  // Developer's Manual Volume 2.
+  emitl(reinterpret_cast<uintptr_t>(value), mode);
+  emitl(0);
+#endif
 }
 
 
 void Assembler::load_rax(ExternalReference ref) {
   load_rax(ref.address(), RelocInfo::EXTERNAL_REFERENCE);
 }
 
 
 void Assembler::leave() {
   EnsureSpace ensure_space(this);
@@ skipping 85 matching lines @@
 
 
 void Assembler::movl(Register dst, Immediate value) {
   EnsureSpace ensure_space(this);
   emit_optional_rex_32(dst);
   emit(0xB8 + dst.low_bits());
   emit(value);
 }
 
 
+#ifdef V8_TARGET_ARCH_X32
+void Assembler::movl(Register dst, int32_t value, RelocInfo::Mode rmode) {
+  // Non-relocatable values might not need a 64-bit representation.
+  if (RelocInfo::IsNone(rmode)) {
+    movl(dst, Immediate(value));
+    return;
+  }
+  EnsureSpace ensure_space(this);
+  emit_optional_rex_32(dst);
+  emit(0xB8 | dst.low_bits());
+  emitl(value, rmode);
+}
+#endif
+
+
 void Assembler::movq(Register dst, const Operand& src) {
   EnsureSpace ensure_space(this);
   emit_rex_64(dst, src);
   emit(0x8B);
   emit_operand(dst, src);
 }
 
 
 void Assembler::movq(Register dst, Register src) {
   EnsureSpace ensure_space(this);
@@ skipping 19 matching lines @@
 
 
 void Assembler::movq(const Operand& dst, Register src) {
   EnsureSpace ensure_space(this);
   emit_rex_64(src, dst);
   emit(0x89);
   emit_operand(src, dst);
 }
 
 
+#ifndef V8_TARGET_ARCH_X32
 void Assembler::movq(Register dst, void* value, RelocInfo::Mode rmode) {
   // This method must not be used with heap object references. The stored
   // address is not GC safe. Use the handle version instead.
   ASSERT(rmode > RelocInfo::LAST_GCED_ENUM);
   EnsureSpace ensure_space(this);
   emit_rex_64(dst);
   emit(0xB8 | dst.low_bits());
   emitq(reinterpret_cast<uintptr_t>(value), rmode);
 }
+#else
+void Assembler::movl(Register dst, void* value, RelocInfo::Mode rmode) {
+  // This method must not be used with heap object references. The stored
+  // address is not GC safe. Use the handle version instead.
+  ASSERT(rmode > RelocInfo::LAST_GCED_ENUM);
+  EnsureSpace ensure_space(this);
+  emit_optional_rex_32(dst);
+  emit(0xB8 | dst.low_bits());
+  emitl(reinterpret_cast<uintptr_t>(value), rmode);
+}
+#endif
 
 
 void Assembler::movq(Register dst, int64_t value, RelocInfo::Mode rmode) {
+#ifndef V8_TARGET_ARCH_X32
   // Non-relocatable values might not need a 64-bit representation.
   if (RelocInfo::IsNone(rmode)) {
     if (is_uint32(value)) {
       movl(dst, Immediate(static_cast<int32_t>(value)));
       return;
     } else if (is_int32(value)) {
       movq(dst, Immediate(static_cast<int32_t>(value)));
       return;
     }
     // Value cannot be represented by 32 bits, so do a full 64 bit immediate
     // value.
   }
+#else
+  ASSERT(RelocInfo::IsNone(rmode));
+  if (is_uint32(value)) {
+    movl(dst, Immediate(static_cast<int32_t>(value)));
+    return;
+  } else if (is_int32(value)) {
+    movq(dst, Immediate(static_cast<int32_t>(value)));
+    return;
+  }
+  // Value cannot be represented by 32 bits, so do a full 64 bit immediate
+  // value.
+#endif
   EnsureSpace ensure_space(this);
   emit_rex_64(dst);
   emit(0xB8 | dst.low_bits());
   emitq(value, rmode);
 }
 
 
+#ifndef V8_TARGET_ARCH_X32
 void Assembler::movq(Register dst, ExternalReference ref) {
   int64_t value = reinterpret_cast<int64_t>(ref.address());
   movq(dst, value, RelocInfo::EXTERNAL_REFERENCE);
 }
+#else
+void Assembler::movl(Register dst, ExternalReference ref) {
+  int32_t value = reinterpret_cast<int32_t>(ref.address());
+  movl(dst, value, RelocInfo::EXTERNAL_REFERENCE);
+}
+#endif
 
 
 void Assembler::movq(const Operand& dst, Immediate value) {
   EnsureSpace ensure_space(this);
   emit_rex_64(dst);
   emit(0xC7);
   emit_operand(0, dst);
   emit(value);
 }
 
@@ skipping 14 matching lines @@
     src->link_to(pc_offset() - sizeof(int32_t));
   } else {
     ASSERT(src->is_unused());
     int32_t current = pc_offset();
     emitl(current);
     src->link_to(current);
   }
 }
 
 
+#ifndef V8_TARGET_ARCH_X32
 void Assembler::movq(Register dst, Handle<Object> value, RelocInfo::Mode mode) {
   AllowDeferredHandleDereference using_raw_address;
   // If there is no relocation info, emit the value of the handle efficiently
   // (possibly using less that 8 bytes for the value).
   if (RelocInfo::IsNone(mode)) {
     // There is no possible reason to store a heap pointer without relocation
     // info, so it must be a smi.
     ASSERT(value->IsSmi());
     movq(dst, reinterpret_cast<int64_t>(*value), RelocInfo::NONE64);
   } else {
     EnsureSpace ensure_space(this);
     ASSERT(value->IsHeapObject());
     ASSERT(!HEAP->InNewSpace(*value));
     emit_rex_64(dst);
     emit(0xB8 | dst.low_bits());
     emitq(reinterpret_cast<uintptr_t>(value.location()), mode);
   }
 }
+#else
+void Assembler::movl(Register dst, Handle<Object> value, RelocInfo::Mode mode) {
+  AllowDeferredHandleDereference using_raw_address;
+  // If there is no relocation info, emit the value of the handle efficiently
+  // (possibly using less that 8 bytes for the value).
+  if (RelocInfo::IsNone(mode)) {
+    // There is no possible reason to store a heap pointer without relocation
+    // info, so it must be a smi.
+    ASSERT(value->IsSmi());
+    movl(dst, reinterpret_cast<int32_t>(*value), RelocInfo::NONE32);
+  } else {
+    EnsureSpace ensure_space(this);
+    ASSERT(value->IsHeapObject());
+    ASSERT(!HEAP->InNewSpace(*value));
+    emit_optional_rex_32(dst);
+    emit(0xB8 | dst.low_bits());
+    emitl(reinterpret_cast<uintptr_t>(value.location()), mode);
+  }
+}
+
+#endif
 
 
 void Assembler::movsxbq(Register dst, const Operand& src) {
   EnsureSpace ensure_space(this);
   emit_rex_64(dst, src);
   emit(0x0F);
   emit(0xBE);
   emit_operand(dst, src);
 }
 
@@ skipping 365 matching lines @@
     emit(0x87);
     emit_modrm(dst, src);
   } else {
     emit_rex_64(src, dst);
     emit(0x87);
     emit_modrm(src, dst);
   }
 }
 
 
+#ifdef V8_TARGET_ARCH_X32
+void Assembler::xchgl(Register dst, Register src) {
+  EnsureSpace ensure_space(this);
+  if (src.is(rax) || dst.is(rax)) {  // Single-byte encoding
+    Register other = src.is(rax) ? dst : src;
+    emit_optional_rex_32(other);
+    emit(0x90 | other.low_bits());
+  } else if (dst.low_bits() == 4) {
+    emit_optional_rex_32(dst, src);
+    emit(0x87);
+    emit_modrm(dst, src);
+  } else {
+    emit_optional_rex_32(src, dst);
+    emit(0x87);
+    emit_modrm(src, dst);
+  }
+}
+#endif
+
+
 void Assembler::store_rax(void* dst, RelocInfo::Mode mode) {
   EnsureSpace ensure_space(this);
+#ifndef V8_TARGET_ARCH_X32
   emit(0x48);  // REX.W
+#endif
   emit(0xA3);
+#ifndef V8_TARGET_ARCH_X32
   emitq(reinterpret_cast<uintptr_t>(dst), mode);
+#else
+  emitl(reinterpret_cast<uintptr_t>(dst), mode);
+  emitl(0);
+#endif
 }
 
 
 void Assembler::store_rax(ExternalReference ref) {
   store_rax(ref.address(), RelocInfo::EXTERNAL_REFERENCE);
 }
 
 
 void Assembler::testb(Register dst, Register src) {
   EnsureSpace ensure_space(this);
@@ skipping 93 matching lines @@
     return;
   }
   EnsureSpace ensure_space(this);
   emit_optional_rex_32(rax, op);
   emit(0xF7);
   emit_operand(rax, op);  // Operation code 0
   emit(mask);
 }
 
 
+#ifdef V8_TARGET_ARCH_X32
+void Assembler::testl(const Operand& op, Register reg) {
+  EnsureSpace ensure_space(this);
+  emit_optional_rex_32(reg, op);
+  emit(0x85);
+  emit_operand(reg, op);
+}
+#endif
+
+
 void Assembler::testq(const Operand& op, Register reg) {
   EnsureSpace ensure_space(this);
   emit_rex_64(reg, op);
   emit(0x85);
   emit_operand(reg, op);
 }
 
 
 void Assembler::testq(Register dst, Register src) {
   EnsureSpace ensure_space(this);
@@ skipping 895 matching lines @@
 
 void Assembler::movmskps(Register dst, XMMRegister src) {
   EnsureSpace ensure_space(this);
   emit_optional_rex_32(dst, src);
   emit(0x0f);
   emit(0x50);
   emit_sse_operand(dst, src);
 }
 
 
+#ifdef V8_TARGET_ARCH_X32
+void Assembler::pcmpeqd(XMMRegister dst, XMMRegister src) {
+  EnsureSpace ensure_space(this);
+  emit(0x66);
+  emit(0x0f);
+  emit(0x76);
+  emit_sse_operand(dst, src);
+}
+#endif
+
+
 void Assembler::emit_sse_operand(XMMRegister reg, const Operand& adr) {
   Register ireg = { reg.code() };
   emit_operand(ireg, adr);
 }
 
 
 void Assembler::emit_sse_operand(XMMRegister dst, XMMRegister src) {
   emit(0xC0 | (dst.low_bits() << 3) | src.low_bits());
 }
 
@@ skipping 68 matching lines @@
 bool RelocInfo::IsCodedSpecially() {
   // The deserializer needs to know whether a pointer is specially coded.  Being
   // specially coded on x64 means that it is a relative 32 bit address, as used
   // by branch instructions.
   return (1 << rmode_) & kApplyMask;
 }
 
 } }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_X64