Fix a warning about inline asm source/destination mismatches for cache_type_register_.

src/base/cpu.cc

 // Copyright 2013 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/base/cpu.h"
 
 #if V8_LIBC_MSVCRT
 #include <intrin.h>  // __cpuid()
 #endif
 #if V8_OS_LINUX
@@ skipping 67 matching lines @@
     || V8_HOST_ARCH_MIPS || V8_HOST_ARCH_MIPS64
 
 #if V8_HOST_ARCH_ARM64
 class CacheLineSizes {
  public:
   CacheLineSizes() {
 #ifdef USE_SIMULATOR
     cache_type_register_ = 0;
 #else
     // Copy the content of the cache type register to a core register.
-    __asm__ __volatile__("mrs %[ctr], ctr_el0"  // NOLINT
+    __asm__ __volatile__("mrs %x[ctr], ctr_el0"  // NOLINT
                          : [ctr] "=r"(cache_type_register_));
 #endif
   }
 
   uint32_t icache_line_size() const { return ExtractCacheLineSize(0); }
   uint32_t dcache_line_size() const { return ExtractCacheLineSize(16); }
 
  private:
   uint32_t ExtractCacheLineSize(int cache_line_size_shift) const {
     // The cache type register holds the size of cache lines in words as a
@@ skipping 627 matching lines @@
       part_ = PPC_POWER5;
       break;
   }
 #endif  // V8_OS_AIX
 #endif  // !USE_SIMULATOR
 #endif  // V8_HOST_ARCH_PPC
 }
 
 }  // namespace base
 }  // namespace v8