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Issue 1784353003: MIPS64: Use BOVC/BNVC for overflow checking on r6. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Created 4 years, 9 months ago
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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. 1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved. 2 // All Rights Reserved.
3 // 3 //
4 // Redistribution and use in source and binary forms, with or without 4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions are 5 // modification, are permitted provided that the following conditions are
6 // met: 6 // met:
7 // 7 //
8 // - Redistributions of source code must retain the above copyright notice, 8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer. 9 // this list of conditions and the following disclaimer.
10 // 10 //
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1365 1365
1366 void Assembler::bne(Register rs, Register rt, int16_t offset) { 1366 void Assembler::bne(Register rs, Register rt, int16_t offset) {
1367 BlockTrampolinePoolScope block_trampoline_pool(this); 1367 BlockTrampolinePoolScope block_trampoline_pool(this);
1368 GenInstrImmediate(BNE, rs, rt, offset); 1368 GenInstrImmediate(BNE, rs, rt, offset);
1369 BlockTrampolinePoolFor(1); // For associated delay slot. 1369 BlockTrampolinePoolFor(1); // For associated delay slot.
1370 } 1370 }
1371 1371
1372 1372
1373 void Assembler::bovc(Register rs, Register rt, int16_t offset) { 1373 void Assembler::bovc(Register rs, Register rt, int16_t offset) {
1374 DCHECK(kArchVariant == kMips64r6); 1374 DCHECK(kArchVariant == kMips64r6);
1375 DCHECK(!(rs.is(zero_reg))); 1375 if (rs.code() >= rt.code()) {
1376 DCHECK(rs.code() >= rt.code()); 1376 GenInstrImmediate(ADDI, rs, rt, offset, CompactBranchType::COMPACT_BRANCH);
1377 GenInstrImmediate(ADDI, rs, rt, offset, CompactBranchType::COMPACT_BRANCH); 1377 } else {
1378 GenInstrImmediate(ADDI, rt, rs, offset, CompactBranchType::COMPACT_BRANCH);
1379 }
1378 } 1380 }
1379 1381
1380 1382
1381 void Assembler::bnvc(Register rs, Register rt, int16_t offset) { 1383 void Assembler::bnvc(Register rs, Register rt, int16_t offset) {
1382 DCHECK(kArchVariant == kMips64r6); 1384 DCHECK(kArchVariant == kMips64r6);
1383 DCHECK(!(rs.is(zero_reg))); 1385 if (rs.code() >= rt.code()) {
1384 DCHECK(rs.code() >= rt.code()); 1386 GenInstrImmediate(DADDI, rs, rt, offset, CompactBranchType::COMPACT_BRANCH);
1385 GenInstrImmediate(DADDI, rs, rt, offset, CompactBranchType::COMPACT_BRANCH); 1387 } else {
1388 GenInstrImmediate(DADDI, rt, rs, offset, CompactBranchType::COMPACT_BRANCH);
1389 }
1386 } 1390 }
1387 1391
1388 1392
1389 void Assembler::blezalc(Register rt, int16_t offset) { 1393 void Assembler::blezalc(Register rt, int16_t offset) {
1390 DCHECK(kArchVariant == kMips64r6); 1394 DCHECK(kArchVariant == kMips64r6);
1391 DCHECK(!(rt.is(zero_reg))); 1395 DCHECK(!(rt.is(zero_reg)));
1392 positions_recorder()->WriteRecordedPositions(); 1396 positions_recorder()->WriteRecordedPositions();
1393 GenInstrImmediate(BLEZ, zero_reg, rt, offset, 1397 GenInstrImmediate(BLEZ, zero_reg, rt, offset,
1394 CompactBranchType::COMPACT_BRANCH); 1398 CompactBranchType::COMPACT_BRANCH);
1395 } 1399 }
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3389 if (icache_flush_mode != SKIP_ICACHE_FLUSH) { 3393 if (icache_flush_mode != SKIP_ICACHE_FLUSH) {
3390 Assembler::FlushICache(isolate, pc, 4 * Assembler::kInstrSize); 3394 Assembler::FlushICache(isolate, pc, 4 * Assembler::kInstrSize);
3391 } 3395 }
3392 } 3396 }
3393 3397
3394 3398
3395 } // namespace internal 3399 } // namespace internal
3396 } // namespace v8 3400 } // namespace v8
3397 3401
3398 #endif // V8_TARGET_ARCH_MIPS64 3402 #endif // V8_TARGET_ARCH_MIPS64
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