[arm64] Fix i/d cache line size confusion typo

src/base/cpu.cc

 // Copyright 2013 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/base/cpu.h"
 
 #if V8_LIBC_MSVCRT
 #include <intrin.h>  // __cpuid()
 #endif
 #if V8_OS_LINUX
@@ skipping 638 matching lines @@
   if (part != NULL) {
     char* end;
     part_ = strtol(part, &end, 0);
     if (end == part) {
       part_ = 0;
     }
     delete[] part;
   }
 
   CacheLineSizes sizes;
-  icache_line_size_ = sizes.dcache_line_size();
-  dcache_line_size_ = sizes.icache_line_size();
+  icache_line_size_ = sizes.icache_line_size();
+  dcache_line_size_ = sizes.dcache_line_size();
 
 #elif V8_HOST_ARCH_PPC
 
 #ifndef USE_SIMULATOR
 #if V8_OS_LINUX
   // Read processor info from /proc/self/auxv.
   char* auxv_cpu_type = NULL;
   FILE* fp = fopen("/proc/self/auxv", "r");
   if (fp != NULL) {
 #if V8_TARGET_ARCH_PPC64
@@ skipping 55 matching lines @@
       part_ = PPC_POWER5;
       break;
   }
 #endif  // V8_OS_AIX
 #endif  // !USE_SIMULATOR
 #endif  // V8_HOST_ARCH_PPC
 }
 
 }  // namespace base
 }  // namespace v8