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Side by Side Diff: src/mips64/macro-assembler-mips64.h

Issue 1779713009: Implement optional turbofan UnalignedLoad and UnalignedStore operators (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Unaligned access simulate using load/shift/or and store/shift/and Created 4 years, 8 months ago
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1 // Copyright 2012 the V8 project authors. All rights reserved. 1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_MIPS_MACRO_ASSEMBLER_MIPS_H_ 5 #ifndef V8_MIPS_MACRO_ASSEMBLER_MIPS_H_
6 #define V8_MIPS_MACRO_ASSEMBLER_MIPS_H_ 6 #define V8_MIPS_MACRO_ASSEMBLER_MIPS_H_
7 7
8 #include "src/assembler.h" 8 #include "src/assembler.h"
9 #include "src/globals.h" 9 #include "src/globals.h"
10 #include "src/mips64/assembler-mips64.h" 10 #include "src/mips64/assembler-mips64.h"
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709 Register scratch = at); 709 Register scratch = at);
710 710
711 void Pref(int32_t hint, const MemOperand& rs); 711 void Pref(int32_t hint, const MemOperand& rs);
712 712
713 713
714 // --------------------------------------------------------------------------- 714 // ---------------------------------------------------------------------------
715 // Pseudo-instructions. 715 // Pseudo-instructions.
716 716
717 void mov(Register rd, Register rt) { or_(rd, rt, zero_reg); } 717 void mov(Register rd, Register rt) { or_(rd, rt, zero_reg); }
718 718
719 void Ulh(Register rd, const MemOperand& rs);
720 void Ulhu(Register rd, const MemOperand& rs);
721 void Ush(Register rd, const MemOperand& rs, Register scratch);
722
719 void Ulw(Register rd, const MemOperand& rs); 723 void Ulw(Register rd, const MemOperand& rs);
724 void Ulwu(Register rd, const MemOperand& rs);
720 void Usw(Register rd, const MemOperand& rs); 725 void Usw(Register rd, const MemOperand& rs);
721 void Uld(Register rd, const MemOperand& rs, Register scratch = at); 726
722 void Usd(Register rd, const MemOperand& rs, Register scratch = at); 727 void Uld(Register rd, const MemOperand& rs);
728 void Usd(Register rd, const MemOperand& rs);
729
730 void Ulwc1(FPURegister fd, const MemOperand& rs, Register scratch);
731 void Uswc1(FPURegister fd, const MemOperand& rs, Register scratch);
732
733 void Uldc1(FPURegister fd, const MemOperand& rs, Register scratch);
734 void Usdc1(FPURegister fd, const MemOperand& rs, Register scratch);
723 735
724 void LoadWordPair(Register rd, const MemOperand& rs, Register scratch = at); 736 void LoadWordPair(Register rd, const MemOperand& rs, Register scratch = at);
725 void StoreWordPair(Register rd, const MemOperand& rs, Register scratch = at); 737 void StoreWordPair(Register rd, const MemOperand& rs, Register scratch = at);
726 738
727 // Load int32 in the rd register. 739 // Load int32 in the rd register.
728 void li(Register rd, Operand j, LiFlags mode = OPTIMIZE_SIZE); 740 void li(Register rd, Operand j, LiFlags mode = OPTIMIZE_SIZE);
729 inline bool LiLower32BitHelper(Register rd, Operand j); 741 inline bool LiLower32BitHelper(Register rd, Operand j);
730 inline void li(Register rd, int64_t j, LiFlags mode = OPTIMIZE_SIZE) { 742 inline void li(Register rd, int64_t j, LiFlags mode = OPTIMIZE_SIZE) {
731 li(rd, Operand(j), mode); 743 li(rd, Operand(j), mode);
732 } 744 }
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2011 #define __FILE_LINE__ __FILE__ ":" CODE_COVERAGE_TOSTRING(__LINE__) 2023 #define __FILE_LINE__ __FILE__ ":" CODE_COVERAGE_TOSTRING(__LINE__)
2012 #define ACCESS_MASM(masm) masm->stop(__FILE_LINE__); masm-> 2024 #define ACCESS_MASM(masm) masm->stop(__FILE_LINE__); masm->
2013 #else 2025 #else
2014 #define ACCESS_MASM(masm) masm-> 2026 #define ACCESS_MASM(masm) masm->
2015 #endif 2027 #endif
2016 2028
2017 } // namespace internal 2029 } // namespace internal
2018 } // namespace v8 2030 } // namespace v8
2019 2031
2020 #endif // V8_MIPS_MACRO_ASSEMBLER_MIPS_H_ 2032 #endif // V8_MIPS_MACRO_ASSEMBLER_MIPS_H_
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