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Side by Side Diff: src/compiler/ppc/instruction-selector-ppc.cc

Issue 1779713009: Implement optional turbofan UnalignedLoad and UnalignedStore operators (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Unaligned access simulate using load/shift/or and store/shift/and Created 4 years, 8 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include "src/base/adapters.h" 5 #include "src/base/adapters.h"
6 #include "src/compiler/instruction-selector-impl.h" 6 #include "src/compiler/instruction-selector-impl.h"
7 #include "src/compiler/node-matchers.h" 7 #include "src/compiler/node-matchers.h"
8 #include "src/compiler/node-properties.h" 8 #include "src/compiler/node-properties.h"
9 #include "src/ppc/frames-ppc.h" 9 #include "src/ppc/frames-ppc.h"
10 10
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317 } else if (g.CanBeImmediate(base, mode)) { 317 } else if (g.CanBeImmediate(base, mode)) {
318 Emit(opcode | AddressingModeField::encode(kMode_MRI), g.NoOutput(), 318 Emit(opcode | AddressingModeField::encode(kMode_MRI), g.NoOutput(),
319 g.UseRegister(offset), g.UseImmediate(base), g.UseRegister(value)); 319 g.UseRegister(offset), g.UseImmediate(base), g.UseRegister(value));
320 } else { 320 } else {
321 Emit(opcode | AddressingModeField::encode(kMode_MRR), g.NoOutput(), 321 Emit(opcode | AddressingModeField::encode(kMode_MRR), g.NoOutput(),
322 g.UseRegister(base), g.UseRegister(offset), g.UseRegister(value)); 322 g.UseRegister(base), g.UseRegister(offset), g.UseRegister(value));
323 } 323 }
324 } 324 }
325 } 325 }
326 326
327 // Architecture supports unaligned access, therefore VisitLoad is used instead
328 void InstructionSelector::VisitUnalignedLoad(Node* node) { UNREACHABLE(); }
329
330 // Architecture supports unaligned access, therefore VisitStore is used instead
331 void InstructionSelector::VisitUnalignedStore(Node* node) { UNREACHABLE(); }
327 332
328 void InstructionSelector::VisitCheckedLoad(Node* node) { 333 void InstructionSelector::VisitCheckedLoad(Node* node) {
329 CheckedLoadRepresentation load_rep = CheckedLoadRepresentationOf(node->op()); 334 CheckedLoadRepresentation load_rep = CheckedLoadRepresentationOf(node->op());
330 PPCOperandGenerator g(this); 335 PPCOperandGenerator g(this);
331 Node* const base = node->InputAt(0); 336 Node* const base = node->InputAt(0);
332 Node* const offset = node->InputAt(1); 337 Node* const offset = node->InputAt(1);
333 Node* const length = node->InputAt(2); 338 Node* const length = node->InputAt(2);
334 ArchOpcode opcode = kArchNop; 339 ArchOpcode opcode = kArchNop;
335 switch (load_rep.representation()) { 340 switch (load_rep.representation()) {
336 case MachineRepresentation::kWord8: 341 case MachineRepresentation::kWord8:
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1933 MachineOperatorBuilder::kFloat64RoundTruncate | 1938 MachineOperatorBuilder::kFloat64RoundTruncate |
1934 MachineOperatorBuilder::kFloat64RoundTiesAway | 1939 MachineOperatorBuilder::kFloat64RoundTiesAway |
1935 MachineOperatorBuilder::kWord32Popcnt | 1940 MachineOperatorBuilder::kWord32Popcnt |
1936 MachineOperatorBuilder::kWord64Popcnt; 1941 MachineOperatorBuilder::kWord64Popcnt;
1937 // We omit kWord32ShiftIsSafe as s[rl]w use 0x3f as a mask rather than 0x1f. 1942 // We omit kWord32ShiftIsSafe as s[rl]w use 0x3f as a mask rather than 0x1f.
1938 } 1943 }
1939 1944
1940 } // namespace compiler 1945 } // namespace compiler
1941 } // namespace internal 1946 } // namespace internal
1942 } // namespace v8 1947 } // namespace v8
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