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Issue 1779713009: Implement optional turbofan UnalignedLoad and UnalignedStore operators (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Unaligned access simulate using load/shift/or and store/shift/and Created 4 years, 8 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
7 7
8 namespace v8 { 8 namespace v8 {
9 namespace internal { 9 namespace internal {
10 namespace compiler { 10 namespace compiler {
(...skipping 76 matching lines...) Expand 10 before | Expand all | Expand 10 after
87 V(MipsTruncUwD) \ 87 V(MipsTruncUwD) \
88 V(MipsTruncUwS) \ 88 V(MipsTruncUwS) \
89 V(MipsCvtDW) \ 89 V(MipsCvtDW) \
90 V(MipsCvtDUw) \ 90 V(MipsCvtDUw) \
91 V(MipsCvtSW) \ 91 V(MipsCvtSW) \
92 V(MipsCvtSUw) \ 92 V(MipsCvtSUw) \
93 V(MipsLb) \ 93 V(MipsLb) \
94 V(MipsLbu) \ 94 V(MipsLbu) \
95 V(MipsSb) \ 95 V(MipsSb) \
96 V(MipsLh) \ 96 V(MipsLh) \
97 V(MipsUlh) \
97 V(MipsLhu) \ 98 V(MipsLhu) \
99 V(MipsUlhu) \
98 V(MipsSh) \ 100 V(MipsSh) \
101 V(MipsUsh) \
99 V(MipsLw) \ 102 V(MipsLw) \
103 V(MipsUlw) \
100 V(MipsSw) \ 104 V(MipsSw) \
105 V(MipsUsw) \
101 V(MipsLwc1) \ 106 V(MipsLwc1) \
107 V(MipsUlwc1) \
102 V(MipsSwc1) \ 108 V(MipsSwc1) \
109 V(MipsUswc1) \
103 V(MipsLdc1) \ 110 V(MipsLdc1) \
111 V(MipsUldc1) \
104 V(MipsSdc1) \ 112 V(MipsSdc1) \
113 V(MipsUsdc1) \
105 V(MipsFloat64ExtractLowWord32) \ 114 V(MipsFloat64ExtractLowWord32) \
106 V(MipsFloat64ExtractHighWord32) \ 115 V(MipsFloat64ExtractHighWord32) \
107 V(MipsFloat64InsertLowWord32) \ 116 V(MipsFloat64InsertLowWord32) \
108 V(MipsFloat64InsertHighWord32) \ 117 V(MipsFloat64InsertHighWord32) \
109 V(MipsFloat64Max) \ 118 V(MipsFloat64Max) \
110 V(MipsFloat64Min) \ 119 V(MipsFloat64Min) \
111 V(MipsFloat32Max) \ 120 V(MipsFloat32Max) \
112 V(MipsFloat32Min) \ 121 V(MipsFloat32Min) \
113 V(MipsPush) \ 122 V(MipsPush) \
114 V(MipsStoreToStackSlot) \ 123 V(MipsStoreToStackSlot) \
(...skipping 16 matching lines...) Expand all
131 #define TARGET_ADDRESSING_MODE_LIST(V) \ 140 #define TARGET_ADDRESSING_MODE_LIST(V) \
132 V(MRI) /* [%r0 + K] */ \ 141 V(MRI) /* [%r0 + K] */ \
133 V(MRR) /* [%r0 + %r1] */ 142 V(MRR) /* [%r0 + %r1] */
134 143
135 144
136 } // namespace compiler 145 } // namespace compiler
137 } // namespace internal 146 } // namespace internal
138 } // namespace v8 147 } // namespace v8
139 148
140 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 149 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
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