Implement optional turbofan UnalignedLoad and UnalignedStore operators

src/mips/macro-assembler-mips.cc

 
 // Copyright 2012 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include <limits.h>  // For LONG_MIN, LONG_MAX.
 
 #if V8_TARGET_ARCH_MIPS
 
 #include "src/base/bits.h"
@@ skipping 1144 matching lines @@
     DCHECK(!tmp.is(rt));
     sll(tmp, rs, sa);
     Addu(rd, rt, tmp);
   }
 }
 
 
 // ------------Pseudo-instructions-------------
 
 void MacroAssembler::Ulw(Register rd, const MemOperand& rs) {
-  lwr(rd, rs);
-  lwl(rd, MemOperand(rs.rm(), rs.offset() + 3));
+  if (is_int16(rs.offset()) && is_int16(rs.offset() + 3)) {
+    if (!rd.is(rs.rm())) {
+      lwr(rd, rs);
+      lwl(rd, MemOperand(rs.rm(), rs.offset() + 3));
+    } else {
+      DCHECK(!rs.rm().is(at));
+      lwr(at, rs);
+      lwl(at, MemOperand(rs.rm(), rs.offset() + 3));
+      mov(rd, at);
+    }
+  } else {  // Offset > 16 bits, use multiple instructions to load.
+    DCHECK(!rd.is(rs.rm()));
+    LoadRegPlusOffsetToAt(rs);
+    lwr(rd, MemOperand(at, 0));
+    lwl(rd, MemOperand(at, 3));
+  }
 }
 
 
 void MacroAssembler::Usw(Register rd, const MemOperand& rs) {
-  swr(rd, rs);
-  swl(rd, MemOperand(rs.rm(), rs.offset() + 3));
+  DCHECK(!rd.is(rs.rm()));
+  if (is_int16(rs.offset()) && is_int16(rs.offset() + 3)) {
+    swr(rd, rs);
+    swl(rd, MemOperand(rs.rm(), rs.offset() + 3));
+  } else {
+    LoadRegPlusOffsetToAt(rs);
+    swr(rd, MemOperand(at, 0));
+    swl(rd, MemOperand(at, 3));
+  }
 }
 
 
 void MacroAssembler::li(Register dst, Handle<Object> value, LiFlags mode) {
   AllowDeferredHandleDereference smi_check;
   if (value->IsSmi()) {
     li(dst, Operand(value), mode);
   } else {
     DCHECK(value->IsHeapObject());
     if (isolate()->heap()->InNewSpace(*value)) {
@@ skipping 4837 matching lines @@
   if (mag.shift > 0) sra(result, result, mag.shift);
   srl(at, dividend, 31);
   Addu(result, result, Operand(at));
 }
 
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_TARGET_ARCH_MIPS