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Side by Side Diff: src/compiler/mips/instruction-codes-mips.h

Issue 1779713009: Implement optional turbofan UnalignedLoad and UnalignedStore operators (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Created 4 years, 9 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
7 7
8 namespace v8 { 8 namespace v8 {
9 namespace internal { 9 namespace internal {
10 namespace compiler { 10 namespace compiler {
(...skipping 69 matching lines...) Expand 10 before | Expand all | Expand 10 after
80 V(MipsTruncUwD) \ 80 V(MipsTruncUwD) \
81 V(MipsTruncUwS) \ 81 V(MipsTruncUwS) \
82 V(MipsCvtDW) \ 82 V(MipsCvtDW) \
83 V(MipsCvtDUw) \ 83 V(MipsCvtDUw) \
84 V(MipsCvtSW) \ 84 V(MipsCvtSW) \
85 V(MipsCvtSUw) \ 85 V(MipsCvtSUw) \
86 V(MipsLb) \ 86 V(MipsLb) \
87 V(MipsLbu) \ 87 V(MipsLbu) \
88 V(MipsSb) \ 88 V(MipsSb) \
89 V(MipsLh) \ 89 V(MipsLh) \
90 V(MipsUlh) \
90 V(MipsLhu) \ 91 V(MipsLhu) \
92 V(MipsUlhu) \
91 V(MipsSh) \ 93 V(MipsSh) \
94 V(MipsUsh) \
92 V(MipsLw) \ 95 V(MipsLw) \
96 V(MipsUlw) \
93 V(MipsSw) \ 97 V(MipsSw) \
98 V(MipsUsw) \
94 V(MipsLwc1) \ 99 V(MipsLwc1) \
95 V(MipsSwc1) \ 100 V(MipsSwc1) \
96 V(MipsLdc1) \ 101 V(MipsLdc1) \
97 V(MipsSdc1) \ 102 V(MipsSdc1) \
98 V(MipsFloat64ExtractLowWord32) \ 103 V(MipsFloat64ExtractLowWord32) \
99 V(MipsFloat64ExtractHighWord32) \ 104 V(MipsFloat64ExtractHighWord32) \
100 V(MipsFloat64InsertLowWord32) \ 105 V(MipsFloat64InsertLowWord32) \
101 V(MipsFloat64InsertHighWord32) \ 106 V(MipsFloat64InsertHighWord32) \
102 V(MipsFloat64Max) \ 107 V(MipsFloat64Max) \
103 V(MipsFloat64Min) \ 108 V(MipsFloat64Min) \
(...skipping 20 matching lines...) Expand all
124 #define TARGET_ADDRESSING_MODE_LIST(V) \ 129 #define TARGET_ADDRESSING_MODE_LIST(V) \
125 V(MRI) /* [%r0 + K] */ \ 130 V(MRI) /* [%r0 + K] */ \
126 V(MRR) /* [%r0 + %r1] */ 131 V(MRR) /* [%r0 + %r1] */
127 132
128 133
129 } // namespace compiler 134 } // namespace compiler
130 } // namespace internal 135 } // namespace internal
131 } // namespace v8 136 } // namespace v8
132 137
133 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 138 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
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