[wasm] Int64Lowering of Int64Add on ia32 and arm.

src/compiler/arm/instruction-selector-arm.cc

Index: src/compiler/arm/instruction-selector-arm.cc
diff --git a/src/compiler/arm/instruction-selector-arm.cc b/src/compiler/arm/instruction-selector-arm.cc
index e0d622891892d0a9e377793be778cde0e201228d..fa5f2151cd91b6edee808ec222f4237eb1b70f99 100644
--- a/src/compiler/arm/instruction-selector-arm.cc
+++ b/src/compiler/arm/instruction-selector-arm.cc
@@ -767,6 +767,23 @@ void InstructionSelector::VisitWord32Sar(Node* node) {
   VisitShift(this, node, TryMatchASR);
 }
 
+void InstructionSelector::VisitInt32PairAdd(Node* node) {
+  ArmOperandGenerator g(this);
+
+  // We use UseUniqueRegister here to avoid register sharing with the temp
+  // register.

[jbramley, 2016/03/11 09:17:05]

In the comment: "... with the output registers."

(There isn't a temp any more.)

[ahaas, 2016/03/14 11:07:50]

Done.

+  InstructionOperand inputs[] = {g.UseUniqueRegister(node->InputAt(0)),
+                                 g.UseUniqueRegister(node->InputAt(1)),
+                                 g.UseUniqueRegister(node->InputAt(2)),
+                                 g.UseUniqueRegister(node->InputAt(3))};

[jbramley, 2016/03/11 09:17:05]

I don't think inputs 0 and 2 have to be unique, since they're only read in the
first instruction. (I could be mistaken.)

[ahaas, 2016/03/14 11:07:50]

Done.

+
+  InstructionOperand outputs[] = {
+      g.DefineAsRegister(node),
+      g.DefineAsRegister(NodeProperties::FindProjection(node, 1))};
+
+  Emit(kArmAddPair, 2, outputs, 4, inputs);
+}
+
 void InstructionSelector::VisitWord32PairShl(Node* node) {
   ArmOperandGenerator g(this);
   Int32Matcher m(node->InputAt(2));