[wasm] Int64Lowering of Int64Add on ia32 and arm.

src/compiler/arm/code-generator-arm.cc

Index: src/compiler/arm/code-generator-arm.cc
diff --git a/src/compiler/arm/code-generator-arm.cc b/src/compiler/arm/code-generator-arm.cc
index a903552edaec5b52034e1dd1937b18d1c1784ffd..8820e994cd118fcbec1e4992a4c5e20698d34098 100644
--- a/src/compiler/arm/code-generator-arm.cc
+++ b/src/compiler/arm/code-generator-arm.cc
@@ -780,6 +780,16 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
       __ teq(i.InputRegister(0), i.InputOperand2(1));
       DCHECK_EQ(SetCC, i.OutputSBit());
       break;
+    case kArmAddPair:
+      // i.InputRegister(0) ... left low word.
+      // i.InputRegister(1) ... left high word.
+      // i.InputRegister(2) ... right low word.
+      // i.InputRegister(3) ... right high word.
+      __ add(i.OutputRegister(0), i.InputRegister(0), i.InputRegister(2),
+             SBit::SetCC);
+      __ adc(i.OutputRegister(1), i.InputRegister(1),
+             Operand(i.InputRegister(3)));

[jbramley, 2016/03/09 10:40:17]

To match other ARM instructions that can't set the flags, consider:
  DCHECK_EQ(LeaveCC, i.OutputSBit());

[jbramley, 2016/03/09 10:40:17]

Consider:
  DCHECK(i.OutputRegister(0), i.InputRegister(1));
  DCHECK(i.OutputRegister(0), i.InputRegister(3));

[ahaas, 2016/03/09 17:28:06]

Done.
These constraints are not needed anymore.

+      break;
     case kArmPairLsl:
       if (instr->InputAt(2)->IsImmediate()) {
         __ PairLsl(i.OutputRegister(0), i.OutputRegister(1), i.InputRegister(0),