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Unified Diff: include/llvm/IR/Intrinsics.td

Issue 17777004: Concurrency support for PNaCl ABI (Closed) Base URL: http://git.chromium.org/native_client/pnacl-llvm.git@master
Patch Set: Fix whitespace. Created 7 years, 6 months ago
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Index: include/llvm/IR/Intrinsics.td
diff --git a/include/llvm/IR/Intrinsics.td b/include/llvm/IR/Intrinsics.td
index 3e496204350e8fc932d2070af8be7a8ea7fff48a..2dfcc8e6b6e467763d20e1da79eb0c5116e6da91 100644
--- a/include/llvm/IR/Intrinsics.td
+++ b/include/llvm/IR/Intrinsics.td
@@ -498,6 +498,46 @@ def int_nacl_tp_tdb_offset : Intrinsic<[llvm_i32_ty], [llvm_i32_ty]>,
// pnaclintrin.h.
def int_nacl_target_arch : Intrinsic<[llvm_i32_ty], []>,
GCCBuiltin<"__builtin_nacl_target_arch">;
+
+// Atomic intrinsics.
+//
+// Volatiles and atomics are encoded through these intrinsics to make
+// them platform-independent, remove some of LLVM's legacy, and isolate
+// PNaCl from future changes to IR. The intrinsics allow user code to
+// use `__sync_*` builtins as well as C11/C++11 atomics.
+//
+// The general signature is:
+// template<typename T>
+// T nacl.atomic.<size>(int32_t operation, T *location, T value,
+// T old_value, int32_t memory_order);
+//
+// Where `T` is a 8, 16, 32 or 64-bit integer (`size` bits), and
+// location is naturally aligned to `T`. Valid `operation` and
+// `memory_order` values are in llvm/IR/NaCl.h.
+//
+// Note that not all arguments are meaningful for all operations:
+// - result = load {atomic|volatile} T* location, align sizeof(T)
+// - store {atomic|volatile} T value, T* location memory_order
+// - result = atomicrmw OP T* location, T value memory_order
+// Where OP is one of: {add, sub, or, and, xor, xchg}
+// - result = cmpxchg T* location, T old_value, T value memory_order
+// - fence memory_order
+def int_nacl_atomic_8 : Intrinsic<[llvm_i8_ty],
+ [llvm_i32_ty, LLVMPointerType<llvm_i8_ty>,
+ llvm_i8_ty, llvm_i8_ty, llvm_i32_ty],
+ [IntrReadWriteArgMem]>;
+def int_nacl_atomic_16 : Intrinsic<[llvm_i16_ty],
+ [llvm_i32_ty, LLVMPointerType<llvm_i16_ty>,
+ llvm_i16_ty, llvm_i16_ty, llvm_i32_ty],
+ [IntrReadWriteArgMem]>;
+def int_nacl_atomic_32 : Intrinsic<[llvm_i32_ty],
+ [llvm_i32_ty, LLVMPointerType<llvm_i32_ty>,
+ llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
+ [IntrReadWriteArgMem]>;
+def int_nacl_atomic_64 : Intrinsic<[llvm_i64_ty],
+ [llvm_i32_ty, LLVMPointerType<llvm_i64_ty>,
+ llvm_i64_ty, llvm_i64_ty, llvm_i32_ty],
+ [IntrReadWriteArgMem]>;
// @LOCALMOD-END
//===----------------------------------------------------------------------===//

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