Concurrency support for PNaCl ABI

include/llvm/IR/Intrinsics.td

 //===- Intrinsics.td - Defines all LLVM intrinsics ---------*- tablegen -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file defines properties of all LLVM intrinsics.
@@ skipping 480 matching lines @@
 def int_nacl_tp_tls_offset : Intrinsic<[llvm_i32_ty], [llvm_i32_ty]>,
                              GCCBuiltin<"__builtin_nacl_tp_tls_offset">;
 def int_nacl_tp_tdb_offset : Intrinsic<[llvm_i32_ty], [llvm_i32_ty]>,
                              GCCBuiltin<"__builtin_nacl_tp_tdb_offset">;
 
 // The following intrinsic provides a target-specific constant value to
 // indicate the target platform compiled to.  The enum values are enumerated
 // pnaclintrin.h.
 def int_nacl_target_arch : Intrinsic<[llvm_i32_ty], []>,
                             GCCBuiltin<"__builtin_nacl_target_arch">;
+
+// Atomic intrinsics.
+//
+// Volatiles and atomics are encoded through these intrinsics to make
+// them platform-independent, remove some of LLVM's legacy, and isolate
+// PNaCl from future changes to IR. The intrinsics allow user code to
+// use `__sync_*` builtins as well as C11/C++11 atomics.
+//
+// The general signature is:
+// template<typename T>
+// T nacl.atomic.<size>(int32_t operation, T *location, T value,
+//                      T old_value, int32_t memory_order);
+//
+// Where `T` is a 8, 16, 32 or 64-bit integer (`size` bits), and
+// location is naturally aligned to `T`. Valid `operation` and
+// `memory_order` values are in llvm/IR/NaCl.h.
+//
+// Note that not all arguments are meaningful for all operations:
+//  - result = load {atomic|volatile} T* location, align sizeof(T)
+//  - store {atomic|volatile} T value, T* location memory_order
+//  - result = atomicrmw OP T* location, T value memory_order
+//    Where OP is one of: {add, sub, or, and, xor, xchg}
+//  - result = cmpxchg T* location, T old_value, T value memory_order
+//  - fence memory_order
+def int_nacl_atomic_8 : Intrinsic<[llvm_i8_ty],
+    [llvm_i32_ty, LLVMPointerType<llvm_i8_ty>,
+    llvm_i8_ty, llvm_i8_ty, llvm_i32_ty],
+    [IntrReadWriteArgMem]>;
+def int_nacl_atomic_16 : Intrinsic<[llvm_i16_ty],
+    [llvm_i32_ty, LLVMPointerType<llvm_i16_ty>,
+    llvm_i16_ty, llvm_i16_ty, llvm_i32_ty],
+    [IntrReadWriteArgMem]>;
+def int_nacl_atomic_32 : Intrinsic<[llvm_i32_ty],
+    [llvm_i32_ty, LLVMPointerType<llvm_i32_ty>,
+    llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
+    [IntrReadWriteArgMem]>;
+def int_nacl_atomic_64 : Intrinsic<[llvm_i64_ty],
+    [llvm_i32_ty, LLVMPointerType<llvm_i64_ty>,
+    llvm_i64_ty, llvm_i64_ty, llvm_i32_ty],
+    [IntrReadWriteArgMem]>;
 // @LOCALMOD-END
 
 //===----------------------------------------------------------------------===//
 // Target-specific intrinsics
 //===----------------------------------------------------------------------===//
 
 include "llvm/IR/IntrinsicsPowerPC.td"
 include "llvm/IR/IntrinsicsX86.td"
 include "llvm/IR/IntrinsicsARM.td"
 include "llvm/IR/IntrinsicsXCore.td"
 include "llvm/IR/IntrinsicsHexagon.td"
 include "llvm/IR/IntrinsicsNVVM.td"
 include "llvm/IR/IntrinsicsMips.td"
 include "llvm/IR/IntrinsicsR600.td"