Improve performance of the malloc shim layer

base/allocator/allocator_shim.cc

Index: base/allocator/allocator_shim.cc
diff --git a/base/allocator/allocator_shim.cc b/base/allocator/allocator_shim.cc
index cc5097ec543cd589afc7e306b6963481b46be2ba..f68903503655605a9d8ac2fdc5ba5909c5be8963 100644
--- a/base/allocator/allocator_shim.cc
+++ b/base/allocator/allocator_shim.cc
@@ -72,8 +72,16 @@ bool CallNewHandler() {
 }
 
 inline const allocator::AllocatorDispatch* GetChainHead() {
+  // TODO(primiano): Just use NoBarrier_Load once crbug.com/593344 is fixed.

[Nico, 2016/03/10 22:50:00]

(filed crbug.com/593874 today and made 3344 blocked on it)

[Primiano Tucci (use gerrit), 2016/03/11 00:11:08]

Seen that. Thanks.

+  // Unfortunately due to that bug NoBarrier_Load() is mistakenly fully
+  // barriered on Linux+Clang, and that causes visible perf regressons.
   return reinterpret_cast<const allocator::AllocatorDispatch*>(
-      subtle::NoBarrier_Load(&g_chain_head));
+#if defined(OS_LINUX) && defined(__clang__)

[Nico, 2016/03/10 22:50:00]

Do we want to check for x86 too?

[Primiano Tucci (use gerrit), 2016/03/11 00:11:08]

Especially for x86, which is where I saw the bug :)

[Nico, 2016/03/11 15:42:04]

I mean on ARM fences are pretty different, so I'm not sure we want the volatile
cast there. (And no idea about mips.)

+      *static_cast<const volatile subtle::AtomicWord*>(&g_chain_head)
+#else
+      subtle::NoBarrier_Load(&g_chain_head)
+#endif
+  );
 }
 
 }  // namespace