Index: src/mips64/simulator-mips64.cc |
diff --git a/src/mips64/simulator-mips64.cc b/src/mips64/simulator-mips64.cc |
index 70c06c885f4637720133fb348b123ea2f7d43044..2e6b0f252a73eeb269a363885ef4c35493cc5e31 100644 |
--- a/src/mips64/simulator-mips64.cc |
+++ b/src/mips64/simulator-mips64.cc |
@@ -3478,9 +3478,7 @@ void Simulator::DecodeTypeRegisterSPECIAL() { |
// Logical right-rotate of a word by a variable number of bits. |
// This is special case od SRLV instruction, added in MIPS32 |
// Release 2. SA field is equal to 00001. |
- alu_out = |
- base::bits::RotateRight32(static_cast<const uint32_t>(rt_u()), |
- static_cast<const uint32_t>(rs_u())); |
+ alu_out = base::bits::RotateRight64(rt_u(), rs_u()); |
} |
SetResult(rd_reg(), alu_out); |
break; |