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Unified Diff: src/mips64/simulator-mips64.cc

Issue 1776623002: MIPS: Fix '[wasm] add rotate opcodes' (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: code clean up according to review. Created 4 years, 9 months ago
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Index: src/mips64/simulator-mips64.cc
diff --git a/src/mips64/simulator-mips64.cc b/src/mips64/simulator-mips64.cc
index 70c06c885f4637720133fb348b123ea2f7d43044..2e6b0f252a73eeb269a363885ef4c35493cc5e31 100644
--- a/src/mips64/simulator-mips64.cc
+++ b/src/mips64/simulator-mips64.cc
@@ -3478,9 +3478,7 @@ void Simulator::DecodeTypeRegisterSPECIAL() {
// Logical right-rotate of a word by a variable number of bits.
// This is special case od SRLV instruction, added in MIPS32
// Release 2. SA field is equal to 00001.
- alu_out =
- base::bits::RotateRight32(static_cast<const uint32_t>(rt_u()),
- static_cast<const uint32_t>(rs_u()));
+ alu_out = base::bits::RotateRight64(rt_u(), rs_u());
}
SetResult(rd_reg(), alu_out);
break;
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