MIPS: Fix '[wasm] add rotate opcodes'

src/mips64/macro-assembler-mips64.cc

Index: src/mips64/macro-assembler-mips64.cc
diff --git a/src/mips64/macro-assembler-mips64.cc b/src/mips64/macro-assembler-mips64.cc
index 831dbc5ac70cfd1daea291be24620e81c6a78127..91b8c9d988807330047cf52db62b73cbacbcd205 100644
--- a/src/mips64/macro-assembler-mips64.cc
+++ b/src/mips64/macro-assembler-mips64.cc
@@ -1225,7 +1225,11 @@ void MacroAssembler::Ror(Register rd, Register rs, const Operand& rt) {
   if (rt.is_reg()) {
     rotrv(rd, rs, rt.rm());
   } else {
-    rotr(rd, rs, rt.imm64_);
+    int64_t ror_value = rt.imm64_ % 32;
+    if (ror_value < 0) {
+      ror_value += 32;
+    }
+    rotr(rd, rs, ror_value);
   }
 }
 
@@ -1234,7 +1238,14 @@ void MacroAssembler::Dror(Register rd, Register rs, const Operand& rt) {
   if (rt.is_reg()) {
     drotrv(rd, rs, rt.rm());
   } else {
-    drotr(rd, rs, rt.imm64_);
+    int64_t shift_value = rt.imm64_;

[akos.palfi.imgtec, 2016/03/09 13:04:21]

Why don't you use the same approach here that you use at Ror(), it would make
the code more consistent.

-    int64_t shift_value = rt.imm64_;
-    if (shift_value < 0) shift_value += 64;
-    if (shift_value >= 64) shift_value -= 64;
+    int64_t shift_value = rt.imm64_ % 64;
+    if (shift_value < 0) {
+      shift_value += 64;
+    }

[Alan Li, 2016/03/09 13:34:35]

Done.

+    if (shift_value < 0) shift_value += 64;
+    if (shift_value >= 64) shift_value -= 64;
+    if (shift_value <= 31) {
+      drotr(rd, rs, shift_value);
+    } else {
+      drotr32(rd, rs, shift_value - 32);
+    }
   }
 }