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Issue 1776623002: MIPS: Fix '[wasm] add rotate opcodes' (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: code clean up according to review. Created 4 years, 9 months ago
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1 // Copyright 2011 the V8 project authors. All rights reserved. 1 // Copyright 2011 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include <limits.h> 5 #include <limits.h>
6 #include <stdarg.h> 6 #include <stdarg.h>
7 #include <stdlib.h> 7 #include <stdlib.h>
8 #include <cmath> 8 #include <cmath>
9 9
10 #if V8_TARGET_ARCH_MIPS64 10 #if V8_TARGET_ARCH_MIPS64
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3471 break; 3471 break;
3472 case DSRLV: 3472 case DSRLV:
3473 if (sa() == 0) { 3473 if (sa() == 0) {
3474 // Regular logical right-shift of a word by a variable number of 3474 // Regular logical right-shift of a word by a variable number of
3475 // bits instruction. SA field is always equal to 0. 3475 // bits instruction. SA field is always equal to 0.
3476 alu_out = rt_u() >> rs(); 3476 alu_out = rt_u() >> rs();
3477 } else { 3477 } else {
3478 // Logical right-rotate of a word by a variable number of bits. 3478 // Logical right-rotate of a word by a variable number of bits.
3479 // This is special case od SRLV instruction, added in MIPS32 3479 // This is special case od SRLV instruction, added in MIPS32
3480 // Release 2. SA field is equal to 00001. 3480 // Release 2. SA field is equal to 00001.
3481 alu_out = 3481 alu_out = base::bits::RotateRight64(rt_u(), rs_u());
3482 base::bits::RotateRight32(static_cast<const uint32_t>(rt_u()),
3483 static_cast<const uint32_t>(rs_u()));
3484 } 3482 }
3485 SetResult(rd_reg(), alu_out); 3483 SetResult(rd_reg(), alu_out);
3486 break; 3484 break;
3487 case SRAV: 3485 case SRAV:
3488 SetResult(rd_reg(), (int32_t)rt() >> rs()); 3486 SetResult(rd_reg(), (int32_t)rt() >> rs());
3489 break; 3487 break;
3490 case DSRAV: 3488 case DSRAV:
3491 SetResult(rd_reg(), rt() >> rs()); 3489 SetResult(rd_reg(), rt() >> rs());
3492 break; 3490 break;
3493 case LSA: { 3491 case LSA: {
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4863 } 4861 }
4864 4862
4865 4863
4866 #undef UNSUPPORTED 4864 #undef UNSUPPORTED
4867 } // namespace internal 4865 } // namespace internal
4868 } // namespace v8 4866 } // namespace v8
4869 4867
4870 #endif // USE_SIMULATOR 4868 #endif // USE_SIMULATOR
4871 4869
4872 #endif // V8_TARGET_ARCH_MIPS64 4870 #endif // V8_TARGET_ARCH_MIPS64
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