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Side by Side Diff: src/compiler/arm/instruction-selector-arm.cc

Issue 1776393004: [wasm] Fixed register allocation for Word32PairShl on arm. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@wasm-add
Patch Set: Created 4 years, 9 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include "src/base/adapters.h" 5 #include "src/base/adapters.h"
6 #include "src/base/bits.h" 6 #include "src/base/bits.h"
7 #include "src/compiler/instruction-selector-impl.h" 7 #include "src/compiler/instruction-selector-impl.h"
8 #include "src/compiler/node-matchers.h" 8 #include "src/compiler/node-matchers.h"
9 #include "src/compiler/node-properties.h" 9 #include "src/compiler/node-properties.h"
10 10
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780 g.DefineAsRegister(node), 780 g.DefineAsRegister(node),
781 g.DefineAsRegister(NodeProperties::FindProjection(node, 1))}; 781 g.DefineAsRegister(NodeProperties::FindProjection(node, 1))};
782 782
783 InstructionOperand temps[] = {g.TempRegister()}; 783 InstructionOperand temps[] = {g.TempRegister()};
784 784
785 Emit(kArmAddPair, 2, outputs, 4, inputs, 1, temps); 785 Emit(kArmAddPair, 2, outputs, 4, inputs, 1, temps);
786 } 786 }
787 787
788 void InstructionSelector::VisitWord32PairShl(Node* node) { 788 void InstructionSelector::VisitWord32PairShl(Node* node) {
789 ArmOperandGenerator g(this); 789 ArmOperandGenerator g(this);
790 // We use g.UseUniqueRegister here for InputAt(0) and InputAt(2) to to
791 // guarantee that there is no register aliasing with output register.
790 Int32Matcher m(node->InputAt(2)); 792 Int32Matcher m(node->InputAt(2));
791 InstructionOperand shift_operand; 793 InstructionOperand shift_operand;
792 if (m.HasValue()) { 794 if (m.HasValue()) {
793 shift_operand = g.UseImmediate(m.node()); 795 shift_operand = g.UseImmediate(m.node());
794 } else { 796 } else {
795 shift_operand = g.UseUniqueRegister(m.node()); 797 shift_operand = g.UseUniqueRegister(m.node());
796 } 798 }
797 799
798 InstructionOperand inputs[] = {g.UseRegister(node->InputAt(0)), 800 InstructionOperand inputs[] = {g.UseUniqueRegister(node->InputAt(0)),
799 g.UseRegister(node->InputAt(1)), 801 g.UseRegister(node->InputAt(1)),
800 shift_operand}; 802 shift_operand};
801 803
802 InstructionOperand outputs[] = { 804 InstructionOperand outputs[] = {
803 g.DefineSameAsFirst(node), 805 g.DefineAsRegister(node),
804 g.DefineAsRegister(NodeProperties::FindProjection(node, 1))}; 806 g.DefineAsRegister(NodeProperties::FindProjection(node, 1))};
805 807
806 Emit(kArmPairLsl, 2, outputs, 3, inputs); 808 Emit(kArmLslPair, 2, outputs, 3, inputs);
807 } 809 }
808 810
809 void InstructionSelector::VisitWord32PairShr(Node* node) { UNIMPLEMENTED(); } 811 void InstructionSelector::VisitWord32PairShr(Node* node) { UNIMPLEMENTED(); }
810 812
811 void InstructionSelector::VisitWord32PairSar(Node* node) { UNIMPLEMENTED(); } 813 void InstructionSelector::VisitWord32PairSar(Node* node) { UNIMPLEMENTED(); }
812 814
813 void InstructionSelector::VisitWord32Ror(Node* node) { 815 void InstructionSelector::VisitWord32Ror(Node* node) {
814 VisitShift(this, node, TryMatchROR); 816 VisitShift(this, node, TryMatchROR);
815 } 817 }
816 818
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1753 MachineOperatorBuilder::kFloat64RoundTiesAway | 1755 MachineOperatorBuilder::kFloat64RoundTiesAway |
1754 MachineOperatorBuilder::kFloat32RoundTiesEven | 1756 MachineOperatorBuilder::kFloat32RoundTiesEven |
1755 MachineOperatorBuilder::kFloat64RoundTiesEven; 1757 MachineOperatorBuilder::kFloat64RoundTiesEven;
1756 } 1758 }
1757 return flags; 1759 return flags;
1758 } 1760 }
1759 1761
1760 } // namespace compiler 1762 } // namespace compiler
1761 } // namespace internal 1763 } // namespace internal
1762 } // namespace v8 1764 } // namespace v8
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