Cache common constants before lowering.

src/IceTargetLoweringX86BaseImpl.h

 //===- subzero/src/IceTargetLoweringX86BaseImpl.h - x86 lowering -*- C++ -*-==//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 1507 matching lines @@
     return false;
   Type Ty = Dest->getType();
   if (Src1 == -1) {
     Variable *T = nullptr;
     _mov(T, Src0);
     _neg(T);
     _mov(Dest, T);
     return true;
   }
   if (Src1 == 0) {
-    _mov(Dest, Ctx->getConstantZero(Ty));
+    _mov(Dest, getConstantZero(Ty));
     return true;
   }
   if (Src1 == 1) {
     Variable *T = nullptr;
     _mov(T, Src0);
     _mov(Dest, T);
     return true;
   }
   // Don't bother with the edge case where Src1 == MININT.
   if (Src1 == -Src1)
@@ skipping 36 matching lines @@
   // somewhat arbitrary choice of 3.
   constexpr uint32_t MaxOpsForOptimizedMul = 3;
   if (CountOps > MaxOpsForOptimizedMul)
     return false;
   Variable *T = makeReg(Traits::WordType);
   if (typeWidthInBytes(Src0->getType()) < typeWidthInBytes(T->getType())) {
     _movzx(T, Src0);
   } else {
     _mov(T, Src0);
   }
-  Constant *Zero = Ctx->getConstantZero(IceType_i32);
+  Constant *Zero = getConstantZero(IceType_i32);
   for (uint32_t i = 0; i < Count9; ++i) {
     constexpr uint16_t Shift = 3; // log2(9-1)
     _lea(T, X86OperandMem::create(Func, IceType_void, T, Zero, T, Shift));
   }
   for (uint32_t i = 0; i < Count5; ++i) {
     constexpr uint16_t Shift = 2; // log2(5-1)
     _lea(T, X86OperandMem::create(Func, IceType_void, T, Zero, T, Shift));
   }
   for (uint32_t i = 0; i < Count3; ++i) {
     constexpr uint16_t Shift = 1; // log2(3-1)
     _lea(T, X86OperandMem::create(Func, IceType_void, T, Zero, T, Shift));
   }
   if (Count2) {
     _shl(T, Ctx->getConstantInt(Ty, Count2));
   }
   if (Src1IsNegative)
     _neg(T);
   _mov(Dest, T);
   return true;
 }
 
 template <typename TraitsType>
 void TargetX86Base<TraitsType>::lowerShift64(InstArithmetic::OpKind Op,
                                              Operand *Src0Lo, Operand *Src0Hi,
                                              Operand *Src1Lo, Variable *DestLo,
                                              Variable *DestHi) {
   // TODO: Refactor the similarities between Shl, Lshr, and Ashr.
   Variable *T_1 = nullptr, *T_2 = nullptr, *T_3 = nullptr;
-  Constant *Zero = Ctx->getConstantZero(IceType_i32);
+  Constant *Zero = getConstantZero(IceType_i32);
   Constant *SignExtend = Ctx->getConstantInt32(0x1f);
   if (auto *ConstantShiftAmount = llvm::dyn_cast<ConstantInteger32>(Src1Lo)) {
     uint32_t ShiftAmount = ConstantShiftAmount->getValue();
     if (ShiftAmount > 32) {
       Constant *ReducedShift = Ctx->getConstantInt32(ShiftAmount - 32);
       switch (Op) {
       default:
         assert(0 && "non-shift op");
         break;
       case InstArithmetic::Shl: {
@@ skipping 569 matching lines @@
       Eax = Traits::RegisterSet::Reg_ax;
       Edx = Traits::RegisterSet::Reg_dx;
       break;
     case IceType_i8:
       Eax = Traits::RegisterSet::Reg_al;
       Edx = Traits::RegisterSet::Reg_ah;
       break;
     }
     T_edx = makeReg(Ty, Edx);
     _mov(T, Src0, Eax);
-    _mov(T_edx, Ctx->getConstantZero(Ty));
+    _mov(T_edx, getConstantZero(Ty));
     _div(T, Src1, T_edx);
     _mov(Dest, T);
   } break;
   case InstArithmetic::Sdiv:
     // TODO(stichnot): Enable this after doing better performance and cross
     // testing.
     if (false && Ctx->getFlags().getOptLevel() >= Opt_1) {
       // Optimize division by constant power of 2, but not for Om1 or O0, just
       // to keep things simple there.
       if (auto *C = llvm::dyn_cast<ConstantInteger32>(Src1)) {
@@ skipping 68 matching lines @@
     case IceType_i16:
       Eax = Traits::RegisterSet::Reg_ax;
       Edx = Traits::RegisterSet::Reg_dx;
       break;
     case IceType_i8:
       Eax = Traits::RegisterSet::Reg_al;
       Edx = Traits::RegisterSet::Reg_ah;
       break;
     }
     T_edx = makeReg(Ty, Edx);
-    _mov(T_edx, Ctx->getConstantZero(Ty));
+    _mov(T_edx, getConstantZero(Ty));
     _mov(T, Src0, Eax);
     _div(T_edx, Src1, T);
     _mov(Dest, T_edx);
   } break;
   case InstArithmetic::Srem: {
     // TODO(stichnot): Enable this after doing better performance and cross
     // testing.
     if (false && Ctx->getFlags().getOptLevel() >= Opt_1) {
       // Optimize mod by constant power of 2, but not for Om1 or O0, just to
       // keep things simple there.
       if (auto *C = llvm::dyn_cast<ConstantInteger32>(Src1)) {
         const int32_t Divisor = C->getValue();
         const uint32_t UDivisor = Divisor;
         if (Divisor > 0 && llvm::isPowerOf2_32(UDivisor)) {
           uint32_t LogDiv = llvm::Log2_32(UDivisor);
           // LLVM does the following for dest=src%(1<<log):
           //   t=src
           //   sar t,typewidth-1 // -1 if src is negative, 0 if not
           //   shr t,typewidth-log
           //   add t,src
           //   and t, -(1<<log)
           //   sub t,src
           //   neg t
           //   dest=t
           uint32_t TypeWidth = Traits::X86_CHAR_BIT * typeWidthInBytes(Ty);
           // If for some reason we are dividing by 1, just assign 0.
           if (LogDiv == 0) {
-            _mov(Dest, Ctx->getConstantZero(Ty));
+            _mov(Dest, getConstantZero(Ty));
             return;
           }
           _mov(T, Src0);
           // The initial sar is unnecessary when dividing by 2.
           if (LogDiv > 1)
             _sar(T, Ctx->getConstantInt(Ty, TypeWidth - 1));
           _shr(T, Ctx->getConstantInt(Ty, TypeWidth - LogDiv));
           _add(T, Src0);
           _and(T, Ctx->getConstantInt(Ty, -(1 << LogDiv)));
           _sub(T, Src0);
@@ skipping 93 matching lines @@
       lowerFcmpAndConsumer(llvm::cast<InstFcmp>(Producer), Br);
       return;
     }
     case BoolFolding<Traits>::PK_Arith: {
       lowerArithAndConsumer(llvm::cast<InstArithmetic>(Producer), Br);
       return;
     }
     }
   }
   Operand *Src0 = legalize(Cond, Legal_Reg | Legal_Mem);
-  Constant *Zero = Ctx->getConstantZero(IceType_i32);
+  Constant *Zero = getConstantZero(IceType_i32);
   _cmp(Src0, Zero);
   _br(Traits::Cond::Br_ne, Br->getTargetTrue(), Br->getTargetFalse());
 }
 
 // constexprMax returns a (constexpr) max(S0, S1), and it is used for defining
 // OperandList in lowerCall. std::max() is supposed to work, but it doesn't.
 inline constexpr SizeT constexprMax(SizeT S0, SizeT S1) {
   return S0 < S1 ? S1 : S0;
 }
 
@@ skipping 278 matching lines @@
     Operand *Src0RM = legalize(Instr->getSrc(0), Legal_Reg | Legal_Mem);
     if (isVectorType(DestTy)) {
       // onemask = materialize(1,1,...); dest = onemask & src
       Variable *OneMask = makeVectorOfOnes(DestTy);
       Variable *T = makeReg(DestTy);
       _movp(T, Src0RM);
       _pand(T, OneMask);
       _movp(Dest, T);
     } else if (!Traits::Is64Bit && DestTy == IceType_i64) {
       // t1=movzx src; dst.lo=t1; dst.hi=0
-      Constant *Zero = Ctx->getConstantZero(IceType_i32);
+      Constant *Zero = getConstantZero(IceType_i32);
       auto *DestLo = llvm::cast<Variable>(loOperand(Dest));
       auto *DestHi = llvm::cast<Variable>(hiOperand(Dest));
       Variable *Tmp = makeReg(DestLo->getType());
       if (Src0RM->getType() == IceType_i32) {
         _mov(Tmp, Src0RM);
       } else {
         _movzx(Tmp, Src0RM);
       }
       _mov(DestLo, Tmp);
       _mov(DestHi, Zero);
@@ skipping 1161 matching lines @@
     Operand *ByteSize = Instr->getArg(0);
     Variable *Dest = Instr->getDest();
     if (auto *CI = llvm::dyn_cast<ConstantInteger32>(ByteSize)) {
       Constant *Result;
       switch (CI->getValue()) {
       default:
         // Some x86-64 processors support the cmpxchg16b instruction, which can
         // make 16-byte operations lock free (when used with the LOCK prefix).
         // However, that's not supported in 32-bit mode, so just return 0 even
         // for large sizes.
-        Result = Ctx->getConstantZero(IceType_i32);
+        Result = getConstantZero(IceType_i32);
         break;
       case 1:
       case 2:
       case 4:
       case 8:
         Result = Ctx->getConstantInt32(1);
         break;
       }
       _mov(Dest, Result);
       return;
@@ skipping 138 matching lines @@
     lowerCall(Call);
     // The popcount helpers always return 32-bit values, while the intrinsic's
     // signature matches the native POPCNT instruction and fills a 64-bit reg
     // (in 64-bit mode). Thus, clear the upper bits of the dest just in case
     // the user doesn't do that in the IR. If the user does that in the IR,
     // then this zero'ing instruction is dead and gets optimized out.
     if (!Traits::Is64Bit) {
       assert(T == Dest);
       if (Val->getType() == IceType_i64) {
         auto *DestHi = llvm::cast<Variable>(hiOperand(Dest));
-        Constant *Zero = Ctx->getConstantZero(IceType_i32);
+        Constant *Zero = getConstantZero(IceType_i32);
         _mov(DestHi, Zero);
       }
     } else {
       assert(Val->getType() == IceType_i64);
       // T is 64 bit. It needs to be copied to dest. We need to:
       //
       // T_1.32 = trunc T.64 to i32
       // T_2.64 = zext T_1.32 to i64
       // Dest.<<right_size>> = T_2.<<right_size>>
       //
@@ skipping 570 matching lines @@
   Variable *T_Dest2 = makeReg(IceType_i32);
   if (Cttz) {
     _bsf(T_Dest2, SecondVar);
   } else {
     _bsr(T_Dest2, SecondVar);
     _xor(T_Dest2, _31);
   }
   _test(SecondVar, SecondVar);
   _cmov(T_Dest2, T_Dest, Traits::Cond::Br_e);
   _mov(DestLo, T_Dest2);
-  _mov(DestHi, Ctx->getConstantZero(IceType_i32));
+  _mov(DestHi, getConstantZero(IceType_i32));
 }
 
 template <typename TraitsType>
 void TargetX86Base<TraitsType>::typedLoad(Type Ty, Variable *Dest,
                                           Variable *Base, Constant *Offset) {
   // If Offset is a ConstantRelocatable in Non-SFI mode, we will need to
   // legalize Mem properly.
   if (Offset)
     assert(!llvm::isa<ConstantRelocatable>(Offset));
 
@@ skipping 785 matching lines @@
   auto *Var = llvm::dyn_cast_or_null<Variable>(Opnd);
   if (Var == nullptr)
     return;
   // We use lowerStore() to copy out-args onto the stack.  This creates a memory
   // operand with the stack pointer as the base register.  Don't do bounds
   // checks on that.
   if (Var->getRegNum() == getStackReg())
     return;
 
   auto *Label = InstX86Label::create(Func, this);
-  _cmp(Opnd, Ctx->getConstantZero(IceType_i32));
+  _cmp(Opnd, getConstantZero(IceType_i32));
   _br(Traits::Cond::Br_e, Label);
   _cmp(Opnd, Ctx->getConstantInt32(1));
   _br(Traits::Cond::Br_e, Label);
   Context.insert(Label);
 }
 
 template <typename TraitsType>
 void TargetX86Base<TraitsType>::lowerLoad(const InstLoad *Load) {
   // A Load instruction can be treated the same as an Assign instruction, after
   // the source operand is transformed into an X86OperandMem operand.  Note that
@@ skipping 73 matching lines @@
       return;
     }
     case BoolFolding<Traits>::PK_Fcmp: {
       lowerFcmpAndConsumer(llvm::cast<InstFcmp>(Producer), Select);
       return;
     }
     }
   }
 
   Operand *CmpResult = legalize(Condition, Legal_Reg | Legal_Mem);
-  Operand *Zero = Ctx->getConstantZero(IceType_i32);
+  Operand *Zero = getConstantZero(IceType_i32);
   _cmp(CmpResult, Zero);
   Operand *SrcT = Select->getTrueOperand();
   Operand *SrcF = Select->getFalseOperand();
   const BrCond Cond = Traits::Cond::Br_ne;
   lowerSelectMove(Dest, Cond, SrcT, SrcF);
 }
 
 template <typename TraitsType>
 void TargetX86Base<TraitsType>::lowerSelectMove(Variable *Dest, BrCond Cond,
                                                 Operand *SrcT, Operand *SrcF) {
@@ skipping 623 matching lines @@
   // during phi lowering assignments
   BoolFlagSaver B(RandomizationPoolingPaused, true);
   PhiLowering::prelowerPhis32Bit<TargetX86Base<TraitsType>>(
       this, Context.getNode(), Func);
 }
 
 template <typename TraitsType>
 void TargetX86Base<TraitsType>::genTargetHelperCallFor(Inst *Instr) {
   uint32_t StackArgumentsSize = 0;
   if (auto *Arith = llvm::dyn_cast<InstArithmetic>(Instr)) {
-    const char *HelperName = nullptr;
+    RuntimeHelperFuncKind HelperName = H_Num;
     Variable *Dest = Arith->getDest();
     Type DestTy = Dest->getType();
     if (!Traits::Is64Bit && DestTy == IceType_i64) {
       switch (Arith->getOp()) {
       default:
         return;
       case InstArithmetic::Udiv:
         HelperName = H_udiv_i64;
         break;
       case InstArithmetic::Sdiv:
@@ skipping 48 matching lines @@
     Call->addArg(Arith->getSrc(1));
     StackArgumentsSize = getCallStackArgumentsSizeBytes(Call);
     Context.insert(Call);
     Arith->setDeleted();
   } else if (auto *Cast = llvm::dyn_cast<InstCast>(Instr)) {
     InstCast::OpKind CastKind = Cast->getCastKind();
     Operand *Src0 = Cast->getSrc(0);
     const Type SrcType = Src0->getType();
     Variable *Dest = Cast->getDest();
     const Type DestTy = Dest->getType();
-    const char *HelperName = nullptr;
+    RuntimeHelperFuncKind HelperName = H_Num;
     Variable *CallDest = Dest;
     switch (CastKind) {
     default:
       return;
     case InstCast::Fptosi:
       if (!Traits::Is64Bit && DestTy == IceType_i64) {
         HelperName = isFloat32Asserting32Or64(SrcType) ? H_fptosi_f32_i64
                                                        : H_fptosi_f64_i64;
       } else {
         return;
@@ skipping 204 matching lines @@
 Variable *TargetX86Base<TraitsType>::makeZeroedRegister(Type Ty,
                                                         RegNumT RegNum) {
   Variable *Reg = makeReg(Ty, RegNum);
   switch (Ty) {
   case IceType_i1:
   case IceType_i8:
   case IceType_i16:
   case IceType_i32:
   case IceType_i64:
     // Conservatively do "mov reg, 0" to avoid modifying FLAGS.
-    _mov(Reg, Ctx->getConstantZero(Ty));
+    _mov(Reg, getConstantZero(Ty));
     break;
   case IceType_f32:
   case IceType_f64:
     Context.insert<InstFakeDef>(Reg);
     _xorps(Reg, Reg);
     break;
   default:
     // All vector types use the same pxor instruction.
     assert(isVectorType(Ty));
     Context.insert<InstFakeDef>(Reg);
@@ skipping 51 matching lines @@
     SizeT Shift =
         typeWidthInBytes(typeElementType(Ty)) * Traits::X86_CHAR_BIT - 1;
     _psll(Reg, Ctx->getConstantInt8(Shift));
     return Reg;
   } else {
     // SSE has no left shift operation for vectors of 8 bit integers.
     constexpr uint32_t HIGH_ORDER_BITS_MASK = 0x80808080;
     Constant *ConstantMask = Ctx->getConstantInt32(HIGH_ORDER_BITS_MASK);
     Variable *Reg = makeReg(Ty, RegNum);
     _movd(Reg, legalize(ConstantMask, Legal_Reg | Legal_Mem));
-    _pshufd(Reg, Reg, Ctx->getConstantZero(IceType_i8));
+    _pshufd(Reg, Reg, getConstantZero(IceType_i8));
     return Reg;
   }
 }
 
 /// Construct a mask in a register that can be and'ed with a floating-point
 /// value to mask off its sign bit. The value will be <4 x 0x7fffffff> for f32
 /// and v4f32, and <2 x 0x7fffffffffffffff> for f64. Construct it as vector of
 /// ones logically right shifted one bit.
 // TODO(stichnot): Fix the wala
 // TODO: above, to represent vector constants in memory.
@@ skipping 291 matching lines @@
     //
     // If in the future the implementation is changed to lower undef values to
     // uninitialized registers, a FakeDef will be needed:
     //     Context.insert<InstFakeDef>(Reg);
     // This is in order to ensure that the live range of Reg is not
     // overestimated.  If the constant being lowered is a 64 bit value, then
     // the result should be split and the lo and hi components will need to go
     // in uninitialized registers.
     if (isVectorType(Ty))
       return makeVectorOfZeros(Ty, RegNum);
-    return Ctx->getConstantZero(Ty);
+    return getConstantZero(Ty);
   }
   return From;
 }
 
 /// For the cmp instruction, if Src1 is an immediate, or known to be a physical
 /// register, we can allow Src0 to be a memory operand. Otherwise, Src0 must be
 /// copied into a physical register. (Actually, either Src0 or Src1 can be
 /// chosen for the physical register, but unfortunately we have to commit to one
 /// or the other before register allocation.)
 template <typename TraitsType>
@@ skipping 501 matching lines @@
         emitGlobal(*Var, SectionSuffix);
       }
     }
   } break;
   }
 }
 } // end of namespace X86NAMESPACE
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASEIMPL_H