Cache common constants before lowering.

src/IceTargetLoweringARM32.cpp

 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 450 matching lines @@
         return;
       }
     }
     switch (DestTy) {
     default:
       return;
     case IceType_i64: {
       // Technically, ARM has its own aeabi routines, but we can use the
       // non-aeabi routine as well. LLVM uses __aeabi_ldivmod for div, but uses
       // the more standard __moddi3 for rem.
-      Operand *TargetHelper = nullptr;
+      RuntimeHelperFuncKind HelperName = H_Num;

[Jim Stichnoth, 2016/03/10 00:24:46]

Nit: it's more of a HelperID than a HelperName.

[Karl, 2016/03/16 22:50:52]

Changed to HelperID.

       switch (Op) {
       default:
         return;
       case InstArithmetic::Udiv:
-        TargetHelper = Ctx->getConstantExternSym(H_udiv_i64);
+        HelperName = H_udiv_i64;
         break;
       case InstArithmetic::Sdiv:
-        TargetHelper = Ctx->getConstantExternSym(H_sdiv_i64);
+        HelperName = H_sdiv_i64;
         break;
       case InstArithmetic::Urem:
-        TargetHelper = Ctx->getConstantExternSym(H_urem_i64);
+        HelperName = H_urem_i64;
         break;
       case InstArithmetic::Srem:
-        TargetHelper = Ctx->getConstantExternSym(H_srem_i64);
+        HelperName = H_srem_i64;
         break;
       }
-      assert(TargetHelper != nullptr);
+      Operand *TargetHelper = getRuntimeHelperFunc(HelperName);
       ARM32HelpersPreamble[TargetHelper] = &TargetARM32::preambleDivRem;
       constexpr SizeT MaxArgs = 2;
       auto *Call = Context.insert<InstCall>(MaxArgs, Dest, TargetHelper,
                                             NoTailCall, IsTargetHelperCall);
       Call->addArg(Instr->getSrc(0));
       Call->addArg(Instr->getSrc(1));
       Instr->setDeleted();
       return;
     }
     case IceType_i32:
     case IceType_i16:
     case IceType_i8: {
       const bool HasHWDiv = hasCPUFeature(TargetARM32Features::HWDivArm);
       InstCast::OpKind CastKind;
-      Operand *TargetHelper;
+      RuntimeHelperFuncKind HelperName = H_Num;
       switch (Op) {
       default:
         return;
       case InstArithmetic::Udiv:
-        TargetHelper =
-            HasHWDiv ? nullptr : Ctx->getConstantExternSym(H_udiv_i32);
+        HelperName = HasHWDiv ? H_Num : H_udiv_i32;
         CastKind = InstCast::Zext;
         break;
       case InstArithmetic::Sdiv:
-        TargetHelper =
-            HasHWDiv ? nullptr : Ctx->getConstantExternSym(H_sdiv_i32);
+        HelperName = HasHWDiv ? H_Num : H_sdiv_i32;
         CastKind = InstCast::Sext;
         break;
       case InstArithmetic::Urem:
-        TargetHelper =
-            HasHWDiv ? nullptr : Ctx->getConstantExternSym(H_urem_i32);
+        HelperName = HasHWDiv ? H_Num : H_urem_i32;
         CastKind = InstCast::Zext;
         break;
       case InstArithmetic::Srem:
-        TargetHelper =
-            HasHWDiv ? nullptr : Ctx->getConstantExternSym(H_srem_i32);
+        HelperName = HasHWDiv ? H_Num : H_srem_i32;
         CastKind = InstCast::Sext;
         break;
       }
-      if (TargetHelper == nullptr) {
-        // TargetHelper should only ever be nullptr when the processor does not
+      if (HelperName == H_Num) {
+        // HelperName should only ever be undefined when the processor does not
         // have a hardware divider. If any other helpers are ever introduced,
         // the following assert will have to be modified.
         assert(HasHWDiv);
         return;
       }
       Operand *Src0 = Instr->getSrc(0);
       Operand *Src1 = Instr->getSrc(1);
       if (DestTy != IceType_i32) {
         // Src0 and Src1 have to be zero-, or signed-extended to i32. For Src0,
         // we just insert a InstCast right before the call to the helper.
@@ skipping 13 matching lines @@
           } else {
             NewC = (NewC << ShAmt) >> ShAmt;
           }
           Src1 = Ctx->getConstantInt32(NewC);
         } else {
           Variable *Src1_32 = Func->makeVariable(IceType_i32);
           Context.insert<InstCast>(CastKind, Src1_32, Src1);
           Src1 = Src1_32;
         }
       }
-      assert(TargetHelper != nullptr);
+      Operand *TargetHelper = getRuntimeHelperFunc(HelperName);
       ARM32HelpersPreamble[TargetHelper] = &TargetARM32::preambleDivRem;
       constexpr SizeT MaxArgs = 2;
       auto *Call = Context.insert<InstCall>(MaxArgs, Dest, TargetHelper,
                                             NoTailCall, IsTargetHelperCall);
       assert(Src0->getType() == IceType_i32);
       Call->addArg(Src0);
       assert(Src1->getType() == IceType_i32);
       Call->addArg(Src1);
       Instr->setDeleted();
       return;
     }
     case IceType_f64:
     case IceType_f32: {
       if (Op != InstArithmetic::Frem) {
         return;
       }
       constexpr SizeT MaxArgs = 2;
-      Operand *TargetHelper = Ctx->getConstantExternSym(
-          DestTy == IceType_f32 ? H_frem_f32 : H_frem_f64);
+      Operand *TargetHelper =
+          getRuntimeHelperFunc(DestTy == IceType_f32 ? H_frem_f32 : H_frem_f64);
       auto *Call = Context.insert<InstCall>(MaxArgs, Dest, TargetHelper,
                                             NoTailCall, IsTargetHelperCall);
       Call->addArg(Instr->getSrc(0));
       Call->addArg(Instr->getSrc(1));
       Instr->setDeleted();
       return;
     }
     }
     llvm::report_fatal_error("Control flow should never have reached here.");
   }
@@ skipping 19 matching lines @@
     switch (CastKind) {
     default:
       return;
     case InstCast::Fptosi:
     case InstCast::Fptoui: {
       if (DestTy != IceType_i64) {
         return;
       }
       const bool DestIsSigned = CastKind == InstCast::Fptosi;
       const bool Src0IsF32 = isFloat32Asserting32Or64(SrcTy);
-      Operand *TargetHelper = Ctx->getConstantExternSym(
+      Operand *TargetHelper = getRuntimeHelperFunc(
           Src0IsF32 ? (DestIsSigned ? H_fptosi_f32_i64 : H_fptoui_f32_i64)
                     : (DestIsSigned ? H_fptosi_f64_i64 : H_fptoui_f64_i64));
       static constexpr SizeT MaxArgs = 1;
       auto *Call = Context.insert<InstCall>(MaxArgs, Dest, TargetHelper,
                                             NoTailCall, IsTargetHelperCall);
       Call->addArg(Src0);
       Instr->setDeleted();
       return;
     }
     case InstCast::Sitofp:
     case InstCast::Uitofp: {
       if (SrcTy != IceType_i64) {
         return;
       }
       const bool SourceIsSigned = CastKind == InstCast::Sitofp;
       const bool DestIsF32 = isFloat32Asserting32Or64(Dest->getType());
-      Operand *TargetHelper = Ctx->getConstantExternSym(
+      Operand *TargetHelper = getRuntimeHelperFunc(
           DestIsF32 ? (SourceIsSigned ? H_sitofp_i64_f32 : H_uitofp_i64_f32)
                     : (SourceIsSigned ? H_sitofp_i64_f64 : H_uitofp_i64_f64));
       static constexpr SizeT MaxArgs = 1;
       auto *Call = Context.insert<InstCall>(MaxArgs, Dest, TargetHelper,
                                             NoTailCall, IsTargetHelperCall);
       Call->addArg(Src0);
       Instr->setDeleted();
       return;
     }
     case InstCast::Bitcast: {
       if (DestTy == SrcTy) {
         return;
       }
       Variable *CallDest = Dest;
-      const char *HelperName = nullptr;
+      RuntimeHelperFuncKind HelperName = H_Num;
       switch (DestTy) {
       default:
         return;
       case IceType_i8:
         assert(SrcTy == IceType_v8i1);
         HelperName = H_bitcast_8xi1_i8;
         CallDest = Func->makeVariable(IceType_i32);
         break;
       case IceType_i16:
         assert(SrcTy == IceType_v16i1);
@@ skipping 10 matching lines @@
       } break;
       case IceType_v16i1: {
         assert(SrcTy == IceType_i16);
         HelperName = H_bitcast_i16_16xi1;
         Variable *Src0AsI32 = Func->makeVariable(stackSlotType());
         // Arguments to functions are required to be at least 32 bits wide.
         Context.insert<InstCast>(InstCast::Zext, Src0AsI32, Src0);
         Src0 = Src0AsI32;
       } break;
       }
-      assert(HelperName != nullptr);
       constexpr SizeT MaxSrcs = 1;
       InstCall *Call = makeHelperCall(HelperName, CallDest, MaxSrcs);
       Call->addArg(Src0);
       Context.insert(Call);
       // The PNaCl ABI disallows i8/i16 return types, so truncate the helper
       // call result to the appropriate type as necessary.
       if (CallDest->getType() != Dest->getType())
         Context.insert<InstCast>(InstCast::Trunc, Dest, CallDest);
       Instr->setDeleted();
       return;
     }
     }
     llvm::report_fatal_error("Control flow should never have reached here.");
   }
   case Inst::IntrinsicCall: {
     Variable *Dest = Instr->getDest();
     auto *IntrinsicCall = llvm::cast<InstIntrinsicCall>(Instr);
     Intrinsics::IntrinsicID ID = IntrinsicCall->getIntrinsicInfo().ID;
     switch (ID) {
     default:
       return;
     case Intrinsics::Ctpop: {
       Operand *Src0 = IntrinsicCall->getArg(0);
-      Operand *TargetHelper = Ctx->getConstantExternSym(
+      Operand *TargetHelper = getRuntimeHelperFunc(
           isInt32Asserting32Or64(Src0->getType()) ? H_call_ctpop_i32
                                                   : H_call_ctpop_i64);
       static constexpr SizeT MaxArgs = 1;
       auto *Call = Context.insert<InstCall>(MaxArgs, Dest, TargetHelper,
                                             NoTailCall, IsTargetHelperCall);
       Call->addArg(Src0);
       Instr->setDeleted();
       if (Src0->getType() == IceType_i64) {
         ARM32HelpersPostamble[TargetHelper] = &TargetARM32::postambleCtpop64;
       }
       return;
     }
     case Intrinsics::Longjmp: {
       static constexpr SizeT MaxArgs = 2;
       static constexpr Variable *NoDest = nullptr;
-      Operand *TargetHelper = Ctx->getConstantExternSym(H_call_longjmp);
+      Operand *TargetHelper = getRuntimeHelperFunc(H_call_longjmp);
       auto *Call = Context.insert<InstCall>(MaxArgs, NoDest, TargetHelper,
                                             NoTailCall, IsTargetHelperCall);
       Call->addArg(IntrinsicCall->getArg(0));
       Call->addArg(IntrinsicCall->getArg(1));
       Instr->setDeleted();
       return;
     }
     case Intrinsics::Memcpy: {
       // In the future, we could potentially emit an inline memcpy/memset, etc.
       // for intrinsic calls w/ a known length.
       static constexpr SizeT MaxArgs = 3;
       static constexpr Variable *NoDest = nullptr;
-      Operand *TargetHelper = Ctx->getConstantExternSym(H_call_memcpy);
+      Operand *TargetHelper = getRuntimeHelperFunc(H_call_memcpy);
       auto *Call = Context.insert<InstCall>(MaxArgs, NoDest, TargetHelper,
                                             NoTailCall, IsTargetHelperCall);
       Call->addArg(IntrinsicCall->getArg(0));
       Call->addArg(IntrinsicCall->getArg(1));
       Call->addArg(IntrinsicCall->getArg(2));
       Instr->setDeleted();
       return;
     }
     case Intrinsics::Memmove: {
       static constexpr SizeT MaxArgs = 3;
       static constexpr Variable *NoDest = nullptr;
-      Operand *TargetHelper = Ctx->getConstantExternSym(H_call_memmove);
+      Operand *TargetHelper = getRuntimeHelperFunc(H_call_memmove);
       auto *Call = Context.insert<InstCall>(MaxArgs, NoDest, TargetHelper,
                                             NoTailCall, IsTargetHelperCall);
       Call->addArg(IntrinsicCall->getArg(0));
       Call->addArg(IntrinsicCall->getArg(1));
       Call->addArg(IntrinsicCall->getArg(2));
       Instr->setDeleted();
       return;
     }
     case Intrinsics::Memset: {
       // The value operand needs to be extended to a stack slot size because the
       // PNaCl ABI requires arguments to be at least 32 bits wide.
       Operand *ValOp = IntrinsicCall->getArg(1);
       assert(ValOp->getType() == IceType_i8);
       Variable *ValExt = Func->makeVariable(stackSlotType());
       Context.insert<InstCast>(InstCast::Zext, ValExt, ValOp);
 
       // Technically, ARM has its own __aeabi_memset, but we can use plain
       // memset too. The value and size argument need to be flipped if we ever
       // decide to use __aeabi_memset.
       static constexpr SizeT MaxArgs = 3;
       static constexpr Variable *NoDest = nullptr;
-      Operand *TargetHelper = Ctx->getConstantExternSym(H_call_memset);
+      Operand *TargetHelper = getRuntimeHelperFunc(H_call_memset);
       auto *Call = Context.insert<InstCall>(MaxArgs, NoDest, TargetHelper,
                                             NoTailCall, IsTargetHelperCall);
       Call->addArg(IntrinsicCall->getArg(0));
       Call->addArg(ValExt);
       Call->addArg(IntrinsicCall->getArg(2));
       Instr->setDeleted();
       return;
     }
     case Intrinsics::NaClReadTP: {
       if (SandboxingType == ST_NaCl) {
         return;
       }
       static constexpr SizeT MaxArgs = 0;
-      const char *ReadTP =
-          SandboxingType == ST_Nonsfi ? "__aeabi_read_tp" : H_call_read_tp;
-      Operand *TargetHelper = Ctx->getConstantExternSym(ReadTP);
+      Operand *TargetHelper = SandboxingType == ST_Nonsfi
+                                  ? Ctx->getConstantExternSym("__aeabi_read_tp")
+                                  : getRuntimeHelperFunc(H_call_read_tp);
       Context.insert<InstCall>(MaxArgs, Dest, TargetHelper, NoTailCall,
                                IsTargetHelperCall);
       Instr->setDeleted();
       return;
     }
     case Intrinsics::Setjmp: {
       static constexpr SizeT MaxArgs = 1;
-      Operand *TargetHelper = Ctx->getConstantExternSym(H_call_setjmp);
+      Operand *TargetHelper = getRuntimeHelperFunc(H_call_setjmp);
       auto *Call = Context.insert<InstCall>(MaxArgs, Dest, TargetHelper,
                                             NoTailCall, IsTargetHelperCall);
       Call->addArg(IntrinsicCall->getArg(0));
       Instr->setDeleted();
       return;
     }
     }
     llvm::report_fatal_error("Control flow should never have reached here.");
   }
   case Inst::Icmp: {
@@ skipping 1905 matching lines @@
       if (ShAmtImm >= 32) {
         if (ShAmtImm == 32) {
           _mov(DestHi, Src0RLo);
         } else {
           Operand *ShAmtOp = shAmtImm(ShAmtImm - 32);
           _lsl(T_Hi, Src0RLo, ShAmtOp);
           _mov(DestHi, T_Hi);
         }
 
         Operand *_0 =
-            legalize(Ctx->getConstantZero(IceType_i32), Legal_Reg | Legal_Flex);
+            legalize(getConstantZero(IceType_i32), Legal_Reg | Legal_Flex);
         _mov(T_Lo, _0);
         _mov(DestLo, T_Lo);
         return;
       }
 
       Variable *Src0RHi = SrcsHi.src0R(this);
       Operand *ShAmtOp = shAmtImm(ShAmtImm);
       Operand *ComplShAmtOp = shAmtImm(32 - ShAmtImm);
       _lsl(T_Hi, Src0RHi, ShAmtOp);
       _orr(T_Hi, T_Hi,
@@ skipping 32 matching lines @@
     // a.hi = t_hi
     //
     // These are incompatible, therefore we mimic pnacl-llc.
     // Can be strength-reduced for constant-shifts, but we don't do that for
     // now.
     // Given the sub/rsb T_C, C.lo, #32, one of the T_C will be negative. On
     // ARM, shifts only take the lower 8 bits of the shift register, and
     // saturate to the range 0-32, so the negative value will saturate to 32.
     Operand *_32 = legalize(Ctx->getConstantInt32(32), Legal_Reg | Legal_Flex);
     Operand *_0 =
-        legalize(Ctx->getConstantZero(IceType_i32), Legal_Reg | Legal_Flex);
+        legalize(getConstantZero(IceType_i32), Legal_Reg | Legal_Flex);
     Variable *T0 = makeReg(IceType_i32);
     Variable *T1 = makeReg(IceType_i32);
     Variable *T2 = makeReg(IceType_i32);
     Variable *TA_Hi = makeReg(IceType_i32);
     Variable *TA_Lo = makeReg(IceType_i32);
     Variable *Src0RLo = SrcsLo.unswappedSrc0R(this);
     Variable *Src0RHi = SrcsHi.unswappedSrc0R(this);
     Variable *Src1RLo = SrcsLo.unswappedSrc1R(this);
     _rsb(T0, Src1RLo, _32);
     _lsr(T1, Src0RLo, T0);
@@ skipping 31 matching lines @@
           } else {
             _lsr(T_Lo, Src0RHi, ShAmtImm);
           }
           _mov(DestLo, T_Lo);
         }
 
         if (ASR) {
           Operand *_31 = shAmtImm(31);
           _asr(T_Hi, Src0RHi, _31);
         } else {
-          Operand *_0 = legalize(Ctx->getConstantZero(IceType_i32),
-                                 Legal_Reg | Legal_Flex);
+          Operand *_0 =
+              legalize(getConstantZero(IceType_i32), Legal_Reg | Legal_Flex);
           _mov(T_Hi, _0);
         }
         _mov(DestHi, T_Hi);
         return;
       }
 
       Variable *Src0RLo = SrcsLo.src0R(this);
       Operand *ShAmtImm = shAmtImm(ShAmt);
       Operand *ComplShAmtImm = shAmtImm(32 - ShAmt);
       _lsr(T_Lo, Src0RLo, ShAmtImm);
@@ skipping 32 matching lines @@
     // orr        t_lo, t_lo, b.hi, lsl t_c1
     // sub        t_c2, c.lo, #32
     // orr        t_lo, t_lo, b.hi, lsr t_c2
     // lsr        t_hi, b.hi, c.lo
     // mov        a.lo, t_lo
     // mov        a.hi, t_hi
     //
     // These are incompatible, therefore we mimic pnacl-llc.
     Operand *_32 = legalize(Ctx->getConstantInt32(32), Legal_Reg | Legal_Flex);
     Operand *_0 =
-        legalize(Ctx->getConstantZero(IceType_i32), Legal_Reg | Legal_Flex);
+        legalize(getConstantZero(IceType_i32), Legal_Reg | Legal_Flex);
     Variable *T0 = makeReg(IceType_i32);
     Variable *T1 = makeReg(IceType_i32);
     Variable *T2 = makeReg(IceType_i32);
     Variable *TA_Lo = makeReg(IceType_i32);
     Variable *TA_Hi = makeReg(IceType_i32);
     Variable *Src0RLo = SrcsLo.unswappedSrc0R(this);
     Variable *Src0RHi = SrcsHi.unswappedSrc0R(this);
     Variable *Src1RLo = SrcsLo.unswappedSrc1R(this);
     _lsr(T0, Src0RLo, Src1RLo);
     _rsb(T1, Src1RLo, _32);
@@ skipping 445 matching lines @@
   }
   case InstArithmetic::Mul: {
     const bool OptM1 = Ctx->getFlags().getOptLevel() == Opt_m1;
     if (!OptM1 && Srcs.hasConstOperand()) {
       constexpr std::size_t MaxShifts = 4;
       std::array<StrengthReduction::AggregationElement, MaxShifts> Shifts;
       SizeT NumOperations;
       int32_t Const = Srcs.getConstantValue();
       const bool Invert = Const < 0;
       const bool MultiplyByZero = Const == 0;
-      Operand *_0 =
-          legalize(Ctx->getConstantZero(DestTy), Legal_Reg | Legal_Flex);
+      Operand *_0 = legalize(getConstantZero(DestTy), Legal_Reg | Legal_Flex);
 
       if (MultiplyByZero) {
         _mov(T, _0);
         _mov(Dest, T);
         return;
       }
 
       if (Invert) {
         Const = -Const;
       }
@@ skipping 499 matching lines @@
       auto *DestLo = llvm::cast<Variable>(loOperand(Dest));
       auto *DestHi = llvm::cast<Variable>(hiOperand(Dest));
       Variable *T_Lo = makeReg(DestLo->getType());
       if (Src0->getType() == IceType_i32) {
         Operand *Src0RF = legalize(Src0, Legal_Reg | Legal_Flex);
         _mov(T_Lo, Src0RF);
       } else if (Src0->getType() != IceType_i1) {
         Variable *Src0R = legalizeToReg(Src0);
         _sxt(T_Lo, Src0R);
       } else {
-        Operand *_0 = Ctx->getConstantZero(IceType_i32);
+        Operand *_0 = getConstantZero(IceType_i32);
         Operand *_m1 = Ctx->getConstantInt32(-1);
         lowerInt1ForSelect(T_Lo, Src0, _m1, _0);
       }
       _mov(DestLo, T_Lo);
       Variable *T_Hi = makeReg(DestHi->getType());
       if (Src0->getType() != IceType_i1) {
         _mov(T_Hi, OperandARM32FlexReg::create(Func, IceType_i32, T_Lo,
                                                OperandARM32::ASR, ShiftAmt));
       } else {
         // For i1, the asr instruction is already done above.
         _mov(T_Hi, T_Lo);
       }
       _mov(DestHi, T_Hi);
     } else if (Src0->getType() != IceType_i1) {
       // t1 = sxt src; dst = t1
       Variable *Src0R = legalizeToReg(Src0);
       Variable *T = makeReg(Dest->getType());
       _sxt(T, Src0R);
       _mov(Dest, T);
     } else {
-      Constant *_0 = Ctx->getConstantZero(IceType_i32);
+      Constant *_0 = getConstantZero(IceType_i32);
       Operand *_m1 = Ctx->getConstantInt(Dest->getType(), -1);
       Variable *T = makeReg(Dest->getType());
       lowerInt1ForSelect(T, Src0, _m1, _0);
       _mov(Dest, T);
     }
     break;
   }
   case InstCast::Zext: {
     if (isVectorType(Dest->getType())) {
       UnimplementedLoweringError(this, Instr);
     } else if (Dest->getType() == IceType_i64) {
       // t1=uxtb src; dst.lo=t1; dst.hi=0
       Operand *_0 =
-          legalize(Ctx->getConstantZero(IceType_i32), Legal_Reg | Legal_Flex);
+          legalize(getConstantZero(IceType_i32), Legal_Reg | Legal_Flex);
       auto *DestLo = llvm::cast<Variable>(loOperand(Dest));
       auto *DestHi = llvm::cast<Variable>(hiOperand(Dest));
       Variable *T_Lo = makeReg(DestLo->getType());
 
       switch (Src0->getType()) {
       default: {
         assert(Src0->getType() != IceType_i64);
         _uxt(T_Lo, legalizeToReg(Src0));
       } break;
       case IceType_i32: {
@@ skipping 332 matching lines @@
 
 void TargetARM32::lowerFcmp(const InstFcmp *Instr) {
   Variable *Dest = Instr->getDest();
   if (isVectorType(Dest->getType())) {
     UnimplementedLoweringError(this, Instr);
     return;
   }
 
   Variable *T = makeReg(IceType_i1);
   Operand *_1 = legalize(Ctx->getConstantInt32(1), Legal_Reg | Legal_Flex);
-  Operand *_0 =
-      legalize(Ctx->getConstantZero(IceType_i32), Legal_Reg | Legal_Flex);
+  Operand *_0 = legalize(getConstantZero(IceType_i32), Legal_Reg | Legal_Flex);
 
   CondWhenTrue Cond = lowerFcmpCond(Instr);
 
   bool RedefineT = false;
   if (Cond.WhenTrue0 != CondARM32::AL) {
     _mov(T, _0);
     RedefineT = true;
   }
 
   if (Cond.WhenTrue0 == CondARM32::kNone) {
@@ skipping 276 matching lines @@
 }
 
 void TargetARM32::lowerIcmp(const InstIcmp *Instr) {
   Variable *Dest = Instr->getDest();
 
   if (isVectorType(Dest->getType())) {
     UnimplementedLoweringError(this, Instr);
     return;
   }
 
-  Operand *_0 =
-      legalize(Ctx->getConstantZero(IceType_i32), Legal_Reg | Legal_Flex);
+  Operand *_0 = legalize(getConstantZero(IceType_i32), Legal_Reg | Legal_Flex);
   Operand *_1 = legalize(Ctx->getConstantInt32(1), Legal_Reg | Legal_Flex);
   Variable *T = makeReg(IceType_i1);
 
   _mov(T, _0);
   CondWhenTrue Cond = lowerIcmpCond(Instr);
   _mov_redefined(T, _1, Cond.WhenTrue0);
   _mov(Dest, T);
 
   assert(Cond.WhenTrue1 == CondARM32::kNone);
 
@@ skipping 35 matching lines @@
 
 void TargetARM32::lowerLoadLinkedStoreExclusive(
     Type Ty, Operand *Addr, std::function<Variable *(Variable *)> Operation,
     CondARM32::Cond Cond) {
 
   auto *Retry = Context.insert<InstARM32Label>(this);
 
   { // scoping for loop highlighting.
     Variable *Success = makeReg(IceType_i32);
     Variable *Tmp = (Ty == IceType_i64) ? makeI64RegPair() : makeReg(Ty);
-    auto *_0 = Ctx->getConstantZero(IceType_i32);
+    auto *_0 = getConstantZero(IceType_i32);
 
     Context.insert<InstFakeDef>(Tmp);
     Context.insert<InstFakeUse>(Tmp);
     Variable *AddrR = legalizeToReg(Addr);
     _ldrex(Tmp, formMemoryOperand(AddrR, Ty))->setDestRedefined();
     auto *StoreValue = Operation(Tmp);
     assert(StoreValue->mustHaveReg());
     // strex requires Dest to be a register other than Value or Addr. This
     // restriction is cleanly represented by adding an "early" definition of
     // Dest (or a latter use of all the sources.)
@@ skipping 144 matching lines @@
   Operand *Arg0 = Instr->getArg(0);
   if (isInt32Asserting32Or64(Arg0->getType())) {
     return;
   }
   // The popcount helpers always return 32-bit values, while the intrinsic's
   // signature matches some 64-bit platform's native instructions and expect to
   // fill a 64-bit reg. Thus, clear the upper bits of the dest just in case the
   // user doesn't do that in the IR or doesn't toss the bits via truncate.
   auto *DestHi = llvm::cast<Variable>(hiOperand(Instr->getDest()));
   Variable *T = makeReg(IceType_i32);
-  Operand *_0 =
-      legalize(Ctx->getConstantZero(IceType_i32), Legal_Reg | Legal_Flex);
+  Operand *_0 = legalize(getConstantZero(IceType_i32), Legal_Reg | Legal_Flex);
   _mov(T, _0);
   _mov(DestHi, T);
 }
 
 void TargetARM32::lowerIntrinsicCall(const InstIntrinsicCall *Instr) {
   Variable *Dest = Instr->getDest();
   Type DestTy = (Dest != nullptr) ? Dest->getType() : IceType_void;
   Intrinsics::IntrinsicID ID = Instr->getIntrinsicInfo().ID;
   switch (ID) {
   case Intrinsics::AtomicFence:
@@ skipping 269 matching lines @@
   }
   case Intrinsics::Memset: {
     llvm::report_fatal_error("memmove should have been prelowered.");
   }
   case Intrinsics::NaClReadTP: {
     if (SandboxingType != ST_NaCl) {
       llvm::report_fatal_error("nacl-read-tp should have been prelowered.");
     }
     Variable *TP = legalizeToReg(OperandARM32Mem::create(
         Func, getPointerType(), getPhysicalRegister(RegARM32::Reg_r9),
-        llvm::cast<ConstantInteger32>(Ctx->getConstantZero(IceType_i32))));
+        llvm::cast<ConstantInteger32>(getConstantZero(IceType_i32))));
     _mov(Dest, TP);
     return;
   }
   case Intrinsics::Setjmp: {
     llvm::report_fatal_error("setjmp should have been prelowered.");
   }
   case Intrinsics::Sqrt: {
     Variable *Src = legalizeToReg(Instr->getArg(0));
     Variable *T = makeReg(Dest->getType());
     _vsqrt(T, Src);
@@ skipping 22 matching lines @@
 
 void TargetARM32::lowerCLZ(Variable *Dest, Variable *ValLoR, Variable *ValHiR) {
   Type Ty = Dest->getType();
   assert(Ty == IceType_i32 || Ty == IceType_i64);
   Variable *T = makeReg(IceType_i32);
   _clz(T, ValLoR);
   if (Ty == IceType_i64) {
     auto *DestLo = llvm::cast<Variable>(loOperand(Dest));
     auto *DestHi = llvm::cast<Variable>(hiOperand(Dest));
     Operand *Zero =
-        legalize(Ctx->getConstantZero(IceType_i32), Legal_Reg | Legal_Flex);
+        legalize(getConstantZero(IceType_i32), Legal_Reg | Legal_Flex);
     Operand *ThirtyTwo =
         legalize(Ctx->getConstantInt32(32), Legal_Reg | Legal_Flex);
     _cmp(ValHiR, Zero);
     Variable *T2 = makeReg(IceType_i32);
     _add(T2, T, ThirtyTwo);
     _clz(T2, ValHiR, CondARM32::NE);
     // T2 is actually a source as well when the predicate is not AL (since it
     // may leave T2 alone). We use _set_dest_redefined to prolong the liveness
     // of T2 as if it was used as a source.
     _set_dest_redefined();
@@ skipping 923 matching lines @@
     // in less predictable code.
     //
     // If in the future the implementation is changed to lower undef values to
     // uninitialized registers, a FakeDef will be needed:
     // Context.insert(InstFakeDef::create(Func, Reg)); This is in order to
     // ensure that the live range of Reg is not overestimated. If the constant
     // being lowered is a 64 bit value, then the result should be split and the
     // lo and hi components will need to go in uninitialized registers.
     if (isVectorType(Ty))
       return makeVectorOfZeros(Ty, RegNum);
-    return Ctx->getConstantZero(Ty);
+    return getConstantZero(Ty);
   }
   return From;
 }
 
 OperandARM32Mem *TargetARM32::formMemoryOperand(Operand *Operand, Type Ty) {
   auto *Mem = llvm::dyn_cast<OperandARM32Mem>(Operand);
   // It may be the case that address mode optimization already creates an
   // OperandARM32Mem, so in that case it wouldn't need another level of
   // transformation.
   if (Mem) {
     return llvm::cast<OperandARM32Mem>(legalize(Mem));
   }
   // If we didn't do address mode optimization, then we only have a
   // base/offset to work with. ARM always requires a base register, so
   // just use that to hold the operand.
   auto *Base = llvm::cast<Variable>(
       legalize(Operand, Legal_Reg | Legal_Rematerializable));
   return OperandARM32Mem::create(
       Func, Ty, Base,
-      llvm::cast<ConstantInteger32>(Ctx->getConstantZero(IceType_i32)));
+      llvm::cast<ConstantInteger32>(getConstantZero(IceType_i32)));
 }
 
 Variable64On32 *TargetARM32::makeI64RegPair() {
   Variable64On32 *Reg =
       llvm::cast<Variable64On32>(Func->makeVariable(IceType_i64));
   Reg->setMustHaveReg();
   Reg->initHiLo(Func);
   Reg->getLo()->setMustNotHaveReg();
   Reg->getHi()->setMustNotHaveReg();
   return Reg;
@@ skipping 202 matching lines @@
   _mov(DestLo, T_Lo);
   if (DestHi) {
     _mov(DestHi, T_Hi);
   }
 }
 
 TargetARM32::SafeBoolChain TargetARM32::lowerInt1(Variable *Dest,
                                                   Operand *Boolean) {
   assert(Boolean->getType() == IceType_i1);
   Variable *T = makeReg(IceType_i1);
-  Operand *_0 =
-      legalize(Ctx->getConstantZero(IceType_i1), Legal_Reg | Legal_Flex);
+  Operand *_0 = legalize(getConstantZero(IceType_i1), Legal_Reg | Legal_Flex);
   Operand *_1 = legalize(Ctx->getConstantInt1(1), Legal_Reg | Legal_Flex);
 
   SafeBoolChain Safe = SBC_Yes;
   if (const Inst *Producer = Computations.getProducerOf(Boolean)) {
     switch (Producer->getKind()) {
     default:
       llvm::report_fatal_error("Unexpected producer.");
     case Inst::Icmp: {
       _mov(T, _0);
       CondWhenTrue Cond = lowerIcmpCond(llvm::cast<InstIcmp>(Producer));
@@ skipping 584 matching lines @@
   // However, for compatibility with current NaCl LLVM, don't claim that.
   Str << ".eabi_attribute 14, 3   @ Tag_ABI_PCS_R9_use: Not used\n";
 }
 
 SmallBitVector TargetARM32::TypeToRegisterSet[RegARM32::RCARM32_NUM];
 SmallBitVector TargetARM32::TypeToRegisterSetUnfiltered[RegARM32::RCARM32_NUM];
 SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM];
 
 } // end of namespace ARM32
 } // end of namespace Ice