Fixes floating point bug in ARM simulator.

runtime/vm/simulator_arm.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include <math.h>  // for isnan.
 #include <setjmp.h>
 #include <stdlib.h>
 
 #include "vm/globals.h"
 #if defined(TARGET_ARCH_ARM)
@@ skipping 742 matching lines @@
   // The sp is initialized to point to the bottom (high address) of the
   // allocated stack area.
   registers_[SP] = StackTop();
   // The lr and pc are initialized to a known bad value that will cause an
   // access violation if the simulator ever tries to execute it.
   registers_[PC] = kBadLR;
   registers_[LR] = kBadLR;
 
   // All double-precision registers are initialized to zero.
   for (int i = 0; i < kNumberOfDRegisters; i++) {
-    dregisters_[i] = 0.0;
+    dregisters_[i] = 0;
   }
   // Since VFP registers are overlapping, single-precision registers should
   // already be initialized.
   ASSERT(2*kNumberOfDRegisters >= kNumberOfSRegisters);
   for (int i = 0; i < kNumberOfSRegisters; i++) {
     ASSERT(sregisters_[i] == 0.0);
   }
   fp_n_flag_ = false;
   fp_z_flag_ = false;
   fp_c_flag_ = false;
@@ skipping 120 matching lines @@
 
 // Raw access to the PC register without the special adjustment when reading.
 int32_t Simulator::get_pc() const {
   return registers_[PC];
 }
 
 
 // Accessors for VFP register state.
 void Simulator::set_sregister(SRegister reg, float value) {
   ASSERT((reg >= 0) && (reg < kNumberOfSRegisters));
+  sregisters_[reg] = bit_cast<int32_t, float>(value);
+}
+
+
+float Simulator::get_sregister(SRegister reg) const {
+  ASSERT((reg >= 0) && (reg < kNumberOfSRegisters));
+  return bit_cast<float, int32_t>(sregisters_[reg]);
+}
+
+
+void Simulator::set_dregister(DRegister reg, double value) {
+  ASSERT((reg >= 0) && (reg < kNumberOfDRegisters));
+  dregisters_[reg] = bit_cast<int64_t, double>(value);
+}
+
+
+double Simulator::get_dregister(DRegister reg) const {
+  ASSERT((reg >= 0) && (reg < kNumberOfDRegisters));
+  return bit_cast<double, int64_t>(dregisters_[reg]);
+}
+
+
+void Simulator::set_sregister_bits(SRegister reg, int32_t value) {
+  ASSERT((reg >= 0) && (reg < kNumberOfSRegisters));
   sregisters_[reg] = value;
 }
 
 
-float Simulator::get_sregister(SRegister reg) const {
+int32_t Simulator::get_sregister_bits(SRegister reg) const {
   ASSERT((reg >= 0) && (reg < kNumberOfSRegisters));
   return sregisters_[reg];
 }
 
 
-void Simulator::set_dregister(DRegister reg, double value) {
+void Simulator::set_dregister_bits(DRegister reg, int64_t value) {
   ASSERT((reg >= 0) && (reg < kNumberOfDRegisters));
   dregisters_[reg] = value;
 }
 
 
-double Simulator::get_dregister(DRegister reg) const {
+int64_t Simulator::get_dregister_bits(DRegister reg) const {
   ASSERT((reg >= 0) && (reg < kNumberOfDRegisters));
   return dregisters_[reg];
 }
 
 
 void Simulator::HandleIllegalAccess(uword addr, Instr* instr) {
   uword fault_pc = get_pc();
   // The debugger will not be able to single step past this instruction, but
   // it will be possible to disassemble the code and inspect registers.
   char buffer[128];
@@ skipping 1433 matching lines @@
 void Simulator::DecodeType6(Instr* instr) {
   if (instr->IsVFPDoubleTransfer()) {
     Register rd = instr->RdField();
     Register rn = instr->RnField();
     if (instr->Bit(8) == 0) {
       SRegister sm = instr->SmField();
       SRegister sm1 = static_cast<SRegister>(sm + 1);
       ASSERT(sm1 < kNumberOfSRegisters);
       if (instr->Bit(20) == 1) {
         // Format(instr, "vmovrrs'cond 'rd, 'rn, {'sm', 'sm1}");
-        set_register(rd, bit_cast<int32_t, float>(get_sregister(sm)));
-        set_register(rn, bit_cast<int32_t, float>(get_sregister(sm1)));
+        set_register(rd, get_sregister_bits(sm));
+        set_register(rn, get_sregister_bits(sm1));
       } else {
         // Format(instr, "vmovsrr'cond {'sm, 'sm1}, 'rd', 'rn");
-        set_sregister(sm, bit_cast<float, int32_t>(get_register(rd)));
-        set_sregister(sm1, bit_cast<float, int32_t>(get_register(rn)));
+        set_sregister_bits(sm, get_register(rd));
+        set_sregister_bits(sm1, get_register(rn));
       }
     } else {
       DRegister dm = instr->DmField();
       if (instr->Bit(20) == 1) {
         // Format(instr, "vmovrrd'cond 'rd, 'rn, 'dm");
-        int64_t dm_val = bit_cast<int64_t, double>(get_dregister(dm));
+        int64_t dm_val = get_dregister_bits(dm);
         set_register(rd, Utils::Low32Bits(dm_val));
         set_register(rn, Utils::High32Bits(dm_val));
       } else {
         // Format(instr, "vmovdrr'cond 'dm, 'rd, 'rn");
         int64_t dm_val = Utils::LowHighTo64Bits(get_register(rd),
                                                 get_register(rn));
-        set_dregister(dm, bit_cast<double, int64_t>(dm_val));
+        set_dregister_bits(dm, dm_val);
       }
     }
   } else if (instr-> IsVFPLoadStore()) {
     Register rn = instr->RnField();
     int32_t addr = get_register(rn);
     int32_t imm_val = instr->Bits(0, 8) << 2;
     if (instr->Bit(23) == 1) {
       addr += imm_val;
     } else {
       addr -= imm_val;
     }
     if (IsIllegalAddress(addr)) {
       HandleIllegalAccess(addr, instr);
     } else {
       if (instr->Bit(8) == 0) {
         SRegister sd = instr->SdField();
         if (instr->Bit(20) == 1) {  // vldrs
           // Format(instr, "vldrs'cond 'sd, ['rn, #+'off10]");
           // Format(instr, "vldrs'cond 'sd, ['rn, #-'off10]");
-          set_sregister(sd, bit_cast<float, int32_t>(ReadW(addr, instr)));
+          set_sregister_bits(sd, ReadW(addr, instr));
         } else {  // vstrs
           // Format(instr, "vstrs'cond 'sd, ['rn, #+'off10]");
           // Format(instr, "vstrs'cond 'sd, ['rn, #-'off10]");
-          WriteW(addr, bit_cast<int32_t, float>(get_sregister(sd)), instr);
+          WriteW(addr, get_sregister_bits(sd), instr);
         }
       } else {
         DRegister dd = instr->DdField();
         if (instr->Bit(20) == 1) {  // vldrd
           // Format(instr, "vldrd'cond 'dd, ['rn, #+'off10]");
           // Format(instr, "vldrd'cond 'dd, ['rn, #-'off10]");
           int64_t dd_val = Utils::LowHighTo64Bits(ReadW(addr, instr),
                                                   ReadW(addr + 4, instr));
-          set_dregister(dd, bit_cast<double, int64_t>(dd_val));
+          set_dregister_bits(dd, dd_val);
         } else {  // vstrd
           // Format(instr, "vstrd'cond 'dd, ['rn, #+'off10]");
           // Format(instr, "vstrd'cond 'dd, ['rn, #-'off10]");
-          int64_t dd_val = bit_cast<int64_t, double>(get_dregister(dd));
+          int64_t dd_val = get_dregister_bits(dd);
           WriteW(addr, Utils::Low32Bits(dd_val), instr);
           WriteW(addr + 4, Utils::High32Bits(dd_val), instr);
         }
       }
     }
   } else if (instr->IsVFPMultipleLoadStore()) {
     Register rn = instr->RnField();
     int32_t addr = get_register(rn);
     int32_t imm_val = instr->Bits(0, 8);
     if (instr->Bit(23) == 0) {
       addr -= (imm_val << 2);
     }
     if (instr->HasW()) {
       if (instr->Bit(23) == 1) {
         set_register(rn, addr + (imm_val << 2));
       } else {
         set_register(rn, addr);  // already subtracted from addr
       }
     }
     if (IsIllegalAddress(addr)) {
       HandleIllegalAccess(addr, instr);
     } else {
       if (instr->Bit(8) == 0) {
         int32_t regs_cnt = imm_val;
         int32_t start = instr->Bit(22) | (instr->Bits(12, 4) << 1);
         for (int i = start; i < start + regs_cnt; i++) {
           SRegister sd = static_cast<SRegister>(i);
           if (instr->Bit(20) == 1) {
             // Format(instr, "vldms'cond'pu 'rn'w, 'slist");
-            set_sregister(sd, bit_cast<float, int32_t>(ReadW(addr, instr)));
+            set_sregister_bits(sd, ReadW(addr, instr));
           } else {
             // Format(instr, "vstms'cond'pu 'rn'w, 'slist");
-            WriteW(addr, bit_cast<int32_t, float>(get_sregister(sd)), instr);
+            WriteW(addr, get_sregister_bits(sd), instr);
           }
           addr += 4;
         }
       } else {
         int32_t regs_cnt = imm_val >> 1;
         int32_t start = (instr->Bit(22) << 4) | instr->Bits(12, 4);
         for (int i = start; i < start + regs_cnt; i++) {
           DRegister dd = static_cast<DRegister>(i);
           if (instr->Bit(20) == 1) {
             // Format(instr, "vldmd'cond'pu 'rn'w, 'dlist");
             int64_t dd_val = Utils::LowHighTo64Bits(ReadW(addr, instr),
                                                     ReadW(addr + 4, instr));
-            set_dregister(dd, bit_cast<double, int64_t>(dd_val));
+            set_dregister_bits(dd, dd_val);
           } else {
             // Format(instr, "vstmd'cond'pu 'rn'w, 'dlist");
-            int64_t dd_val = bit_cast<int64_t, double>(get_dregister(dd));
+            int64_t dd_val = get_dregister_bits(dd);
             WriteW(addr, Utils::Low32Bits(dd_val), instr);
             WriteW(addr + 4, Utils::High32Bits(dd_val), instr);
           }
           addr += 8;
         }
       }
     }
   } else {
     UnimplementedInstruction(instr);
   }
@@ skipping 230 matching lines @@
                 set_dregister(dd, static_cast<double>(get_sregister(sm)));
               } else {
                 // Format(instr, "vcvtsd'cond 'sd, 'dm");
                 sd = instr->SdField();
                 set_sregister(sd, static_cast<float>(get_dregister(dm)));
               }
               break;
             }
             case 8: {  // vcvt, vcvtr between floating-point and integer
               sm = instr->SmField();
-              float sm_val = get_sregister(sm);
+              int32_t sm_int = get_sregister_bits(sm);
               uint32_t ud_val = 0;
               int32_t id_val = 0;
               if (instr->Bit(7) == 0) {  // vcvtsu, vcvtdu
-                ud_val = bit_cast<uint32_t, float>(sm_val);
+                ud_val = static_cast<uint32_t>(sm_int);
               } else {  // vcvtsi, vcvtdi
-                id_val = bit_cast<int32_t, float>(sm_val);
+                id_val = sm_int;
               }
               if (instr->Bit(8) == 0) {
                 float sd_val;
                 if (instr->Bit(7) == 0) {
                   // Format(instr, "vcvtsu'cond 'sd, 'sm");
                   sd_val = static_cast<float>(ud_val);
                 } else {
                   // Format(instr, "vcvtsi'cond 'sd, 'sm");
                   sd_val = static_cast<float>(id_val);
                 }
@@ skipping 57 matching lines @@
                   if (dm_val <= INT_MIN) {
                     id_val = INT_MIN;
                   } else if (dm_val >= INT_MAX) {
                     id_val = INT_MAX;
                   } else {
                     id_val = static_cast<int32_t>(dm_val);
                   }
                   ASSERT((id_val >= 0) || !(dm_val >= 0.0));
                 }
               }
-              float sd_val;
+              int32_t sd_val;
               if (instr->Bit(16) == 0) {
-                sd_val = bit_cast<float, uint32_t>(ud_val);
+                sd_val = static_cast<int32_t>(ud_val);
               } else {
-                sd_val = bit_cast<float, int32_t>(id_val);
+                sd_val = id_val;
               }
-              set_sregister(sd, sd_val);
+              set_sregister_bits(sd, sd_val);
               break;
             }
             case 2:  // vcvtb, vcvtt
             case 3:  // vcvtb, vcvtt
             case 9:  // undefined
             case 10:  // vcvt between floating-point and fixed-point
             case 11:  // vcvt between floating-point and fixed-point
             case 14:  // vcvt between floating-point and fixed-point
             case 15:  // vcvt between floating-point and fixed-point
             default: {
               UnimplementedInstruction(instr);
               break;
             }
           }
         }
         break;
       }
     } else {
       // 8, 16, or 32-bit Transfer between ARM Core and VFP
       if ((instr->Bits(21, 3) == 0) && (instr->Bit(8) == 0)) {
         Register rd = instr->RdField();
         SRegister sn = instr->SnField();
         if (instr->Bit(20) == 0) {
           // Format(instr, "vmovs'cond 'sn, 'rd");
-          set_sregister(sn, bit_cast<float, int32_t>(get_register(rd)));
+          set_sregister_bits(sn, get_register(rd));
         } else {
           // Format(instr, "vmovr'cond 'rd, 'sn");
-          set_register(rd, bit_cast<int32_t, float>(get_sregister(sn)));
+          set_register(rd, get_sregister_bits(sn));
         }
       } else if ((instr->Bits(20, 4) == 0xf) && (instr->Bit(8) == 0) &&
                  (instr->Bits(12, 4) == 0xf)) {
         // Format(instr, "vmstat'cond");
         n_flag_ = fp_n_flag_;
         z_flag_ = fp_z_flag_;
         c_flag_ = fp_c_flag_;
         v_flag_ = fp_v_flag_;
       } else {
         UnimplementedInstruction(instr);
@@ skipping 235 matching lines @@
   set_register(kExceptionObjectReg, bit_cast<int32_t>(raw_exception));
   set_register(kStackTraceObjectReg, bit_cast<int32_t>(raw_stacktrace));
   buf->Longjmp();
 }
 
 }  // namespace dart
 
 #endif  // !defined(HOST_ARCH_ARM)
 
 #endif  // defined TARGET_ARCH_ARM